Re: [PATCH 2/6] x86/vpmu: Expose PEBS and DS area in PV mode

["Teddy Astie" <teddy.astie@xxxxxxxxxx>]

Le 24/03/2026 à 10:14, Jan Beulich a écrit :
> On 10.03.2026 17:44, Teddy Astie wrote:
>> I don't see any reason for them for not be available, especially
>> since core2_vpmu_do_wrmsr has PV specific logic for MSR_IA32_DS_AREA.
>
> This is really dangerous: You allow PV domains to control whether the area
> is actually mapped. It lacking a mapping can, iirc, on at least some CPUs
> result in a complete hang. I do, in fact, have been carrying a patch to
> completely disallow DS area use for PV, eliminating the misleading code
> you refer to.
>

While PV case is particularly quirky (especially with L1TF), the issues
still exists for HVM.
I suppose things may be a bit better with "EPT-Friendly PEBS" though.

Regardless, we already say that the feature is potentially unsafe to
use, and it still needs to be opted-in, so this patch just allows the
guest to use something we advertise (with its eventual quirks).

> Also note that VPMU_CPU_HAS_DS cannot be set for PV vCPU-s anyway.
>

Why is that ?

`vpmu_set(vpmu, VPMU_CPU_HAS_DS);` made in core2_vpmu_initialise is
called in either PV and HVM cases.

>> Fixes: 27c554198666 ("x86/VPMU: add support for PMU register handling on PV 
>> guests")
>
> Not just because of the above, I'm pretty sure a Fixes: tag is inappropriate
> here.
>
> Jan
>

Teddy


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