[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v4 2/2] ns16550: add support for ASIX AX99100 PCIe Multi-I/O controller
- To: Jiaqing Zhao <Zhao.Jiaqing@xxxxxxx>
- From: Roger Pau Monné <roger.pau@xxxxxxxxxx>
- Date: Tue, 2 Jun 2026 09:09:47 +0200
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=citrix.com; dmarc=pass action=none header.from=citrix.com; dkim=pass header.d=citrix.com; arc=none
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=yzBOkVaS5wdUjfIL1Ju9DNol10hvtzZYhFiphFE6mlc=; b=SKQc2jSypIyqqydWm1wwwGpoUWdchivX6Xyb7vj00Lhnkkors9utS7KsEa8oTBjSCWXcddal+rseh/Ho6oY9Yf8qVtFm9cxxUyMa8uQoIP30v4DY6TQe1tX1hrCwBmzQpuPaTXKSDGVC8sg/ermV+fpdZikp1nZ86CCsPRBdqOJ8lAtqfglYpcYPnyWW4jyGajAAnHhEbE0E/whMpIlLHsXi7DBl9PY7QU+S7/LF4Kgb1cfhE5H5WcfxltZYPsYhP4aU18zBDXInO4lQpwKyZVcQ3d8hxSxnRZM0NReu2y2I3JxkFnm/pIhYd+SS24CLJtEuepLbea8uDNaMC2KpGw==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=rklgMrdFLBEa8WMCtjA/CorMu9VoCZsOl5zO4r66l6CPPA612iF9PFQM91wTqNRTxT/OGWOLXAnv3STptM+ZxdvE4g6YEHnLInvsvLXrk8WyM00a1MsaUfUvdFYObo4k4ZZb849CUq7wY3bfK46sWXfXJHl0H83JUXj2m8O1CrxpKQkzbYFmj0eiuDFZ/j8aPAUH4rafl9mYN65Z6Z2vegWU9Nwa3Kbudl1Qcya48YX9FDlk1Ly0SB4GqXUg9NpE3UYakYZafa17mwG+mW3USGEuxiwS54u5e5qlKa7Qa5V1zuv3OyRLUSCD+154itZlXLqHf91HDqfP4PLYpWemBQ==
- Authentication-results: eu.smtp.expurgate.cloud; dkim=pass header.s=selector1 header.d=citrix.com header.i="@citrix.com" header.h="From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck"
- Authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=citrix.com;
- Cc: xen-devel@xxxxxxxxxxxxxxxxxxxx, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Anthony PERARD <anthony.perard@xxxxxxxxxx>, Michal Orzel <michal.orzel@xxxxxxx>, Jan Beulich <jbeulich@xxxxxxxx>, Julien Grall <julien@xxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>
- Delivery-date: Tue, 02 Jun 2026 07:09:58 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On Tue, Jun 02, 2026 at 01:34:21PM +0800, Jiaqing Zhao wrote:
> Add a PCI device table entry and matching parameter for the ASIX
> AX99100 PCIe to Multi-I/O controller [125b:9910]. Each port on the
> chip is a standalone PCI function, with UART registers on its I/O
> BAR0.
>
> Signed-off-by: Jiaqing Zhao <Zhao.Jiaqing@xxxxxxx>
> Reviewed-by: Stefano Stabellini <sstabellini@xxxxxxxxxx>
> ---
> xen/drivers/char/ns16550.c | 15 +++++++++++++++
> xen/include/xen/pci_ids.h | 2 ++
> 2 files changed, 17 insertions(+)
>
> diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c
> index cf10a06a3d..26503070dc 100644
> --- a/xen/drivers/char/ns16550.c
> +++ b/xen/drivers/char/ns16550.c
> @@ -96,6 +96,7 @@ struct ns16550_config {
> param_exar_xr17v358,
> param_intel_lpss,
> param_wch_ch382,
> + param_asix,
> } param;
> };
>
> @@ -872,6 +873,14 @@ static const struct ns16550_config_param __initconst
> uart_param[] = {
> .bar0 = 1,
> .max_ports = 2,
> },
> + [param_asix] = {
> + .base_baud = 115200,
> + .reg_width = 1,
> + .fifo_size = 256,
> + .lsr_mask = UART_LSR_THRE,
> + .bar0 = 1,
Same comment about using 1 instead of true, the rest seem reasonable:
Acked-by: Roger Pau Monné <roger.pau@xxxxxxxxxx>
Thanks, Roger.
|
