Re: [Xen-devel][PATCH]Fix the read error from IRR,ISR and TMR

[Keir Fraser <Keir.Fraser@xxxxxxxxxxxx>]

On 31/8/06 8:47 am, "Xin, Xiaohui" <xiaohui.xin@xxxxxxxxx> wrote:

> Since from SDM3 spec, for APIC registers, all 32-bit registers should be
> accessed using 128-bit aligned 32bit loads or stores.
> 
> And wider registers (64-bit or 256-bit) must be accessed using multiple
> 32-bit loads or stores.
> 
> In old APIC virtualization code, we use IRR, ISR and TMR which are
> 256-bit registers as contiguous bit maps other than multiple 32-bit.

SDM3 is not at all clear that these bitmaps are 8 32-bit registers rather
than a single 256-bit register. In fact, the manual makes it look very much
like they are the latter (e.g., by saying that some registers are 256 bits,
and that access to secondary 32-bit subwords happen at non-128-bit aligned
addresses), which is very misleading!

Yet another example where the manuals provide heaps of obvious and redundant
info (like explaining that APIC registers are not MSRs -- duh!) but being
ambiguous or misleading on subtle but essential details like this.

Since it turns out that *all* registers are 128-bit aligned and 32-bits, I
think the regs block should be changed to be an array of 32-bit registers,
skipping the unused parts of the APIC page (i.e., so that register x can be
found by regs[x>>4]). Then the bitmaps would be conveniently contiguous
again! And since the array would be only 1kB, it would mean we can get rid
of the alloc_domheap_page() and map_domain_page_global().

 -- Keir



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