[Xen-devel] [PATCH] CPUIDLE: revise tsc-save/restore to avoid big tsc skew between cpus

["Wei, Gang" <gang.wei@xxxxxxxxx>]

Originally, the sequence for each cpu is [tsc-save, entry deepC, break-evt, 
exit deepC, tsc-restore], the system error is quite easy to be accumulated. 
Once the workloads between cpus are not balanced, the tsc skew between cpus 
will eventually become bigger & begger - more than 10 seconds can be observed.

Now, we just keep a initial stamp via cstate_init_stamp during the booting/s3 
resuming, which is based on the platform stime. All cpus need only to do 
tsc-restore relative to the initial stamp after exit deepC. The base is fixed, 
and is the same for all cpus, so it can avoid accumulated tsc-skew.

Signed-off-by: Wei Gang <gang.wei@xxxxxxxxx>

Attachment: tsc-skew-20081205-2.patch
Description: tsc-skew-20081205-2.patch

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