[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [Xen-devel] intel IGD driver intel_detect_pch() failure
On Fri, Dec 14, 2012 at 10:39 AM, G.R. <firemeteor@xxxxxxxxxxxxxxxxxxxxx> wrote: > On Fri, Dec 14, 2012 at 1:39 AM, G.R. <firemeteor@xxxxxxxxxxxxxxxxxxxxx> > wrote: >> On Thu, Dec 13, 2012 at 10:33 PM, G.R. <firemeteor@xxxxxxxxxxxxxxxxxxxxx> >> wrote: >>> On Thu, Dec 13, 2012 at 8:43 PM, Stefano Stabellini >>> <stefano.stabellini@xxxxxxxxxxxxx> wrote: >>>> >>>> Does this patch work for you? >>>> >>> >>> It appears that you change the exposed 1f.0 bridge into an ISA bridge. >>> The driver should be able to recognize it -- as long as it is not >>> hidden by the PIIX3 bridge. >>> I wonder if there is way to entirely override that one... >>> But anyway I'll try it out first. >>> >> >> Stefano, your patch does not produce an ISA bridge as expected. >> The device as viewed from the domU is like this: >> 00:1f.0 Non-VGA unclassified device [0000]: Intel Corporation H77 >> Express Chipset LPC Controller [8086:1e4a] (rev 04) >> >> I'm on the latest 4.2-testing branch just synced && built for your patch. >> > > Some more info from lspci: > > Intel ISA bridge as seen from dom0: > 00:1f.0 ISA bridge: Intel Corporation H77 Express Chipset LPC > Controller (rev 04) > 00: 86 80 4a 1e 07 00 10 02 04 00 01 06 00 00 80 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 49 18 4a 1e > 30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 > > After exposed to domU > 00:1f.0 Non-VGA unclassified device: Intel Corporation H77 Express > Chipset LPC Controller (rev 04) > 00: 86 80 4a 1e 07 00 a0 00 04 00 01 06 00 10 81 00 > 10: 00 50 42 f1 10 50 42 f1 00 01 01 f1 30 50 42 f1 > 20: 40 50 42 f1 50 50 42 f1 00 00 00 00 f4 1a 00 11 > 30: 60 50 42 f1 00 00 00 00 00 00 00 00 00 00 00 00 > > The PIIX3 ISA bridge as emulated by qemu: > > 00:01.0 ISA bridge: Intel Corporation 82371SB PIIX3 ISA [Natoma/Triton II] > 00: 86 80 00 70 07 00 00 02 00 00 01 06 00 00 80 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 f4 1a 00 11 > 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > I have no idea if this is due to the header type set to 0x81 (pci-pci > bridge, multi-functional), or some other fields need to be cleared... > I did another experiment to change the header type to 0x80. The devices now shows up as an ISA bridge. But as long as the PIIX3 bridge cannot be overridden, I need another hack in intel driver to make it work. This is the local hack I made, based on kernel 3.2.31. But the function does not change in new version, other than new chip support. Not sure if this change is acceptable to upstream... --- i915_drv.c.orig 2012-10-10 10:31:37.000000000 +0800 +++ i915_drv.c 2012-12-14 19:10:32.000000000 +0800 @@ -303,6 +303,7 @@ { struct drm_i915_private *dev_priv = dev->dev_private; struct pci_dev *pch; + unsigned found = 0; /* * The reason to probe ISA bridge instead of Dev31:Fun0 is to @@ -311,11 +312,13 @@ * underneath. This is a requirement from virtualization team. */ pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); - if (pch) { + while (pch) { if (pch->vendor == PCI_VENDOR_ID_INTEL) { int id; id = pch->device & INTEL_PCH_DEVICE_ID_MASK; + found = pch->device; + if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { dev_priv->pch_type = PCH_IBX; DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); @@ -326,9 +329,21 @@ /* PantherPoint is CPT compatible */ dev_priv->pch_type = PCH_CPT; DRM_DEBUG_KMS("Found PatherPoint PCH\n"); + } else { + found = 0; } + } + if (found) { + pci_dev_put(pch); + break; + } else { + struct pci_dev *curr = pch; + pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, curr); + pci_dev_put(curr); } - pci_dev_put(pch); + } + if (!found) { + DRM_DEBUG_KMS("intel PCH detect failed, nothing found\n"); } } > >> Thanks, >> Timothy >> >>>> >>>> >>>> diff --git a/hw/pci.c b/hw/pci.c >>>> index f051de1..d371bd7 100644 >>>> --- a/hw/pci.c >>>> +++ b/hw/pci.c >>>> @@ -871,11 +871,6 @@ void pci_unplug_netifs(void) >>>> } >>>> } >>>> >>>> -typedef struct { >>>> - PCIDevice dev; >>>> - PCIBus *bus; >>>> -} PCIBridge; >>>> - >>>> void pci_bridge_write_config(PCIDevice *d, >>>> uint32_t address, uint32_t val, int len) >>>> { >>>> diff --git a/hw/pci.h b/hw/pci.h >>>> index edc58b6..c2acab9 100644 >>>> --- a/hw/pci.h >>>> +++ b/hw/pci.h >>>> @@ -222,6 +222,11 @@ struct PCIDevice { >>>> int irq_state[4]; >>>> }; >>>> >>>> +typedef struct { >>>> + PCIDevice dev; >>>> + PCIBus *bus; >>>> +} PCIBridge; >>>> + >>>> extern char direct_pci_str[]; >>>> extern int direct_pci_msitranslate; >>>> extern int direct_pci_power_mgmt; >>>> diff --git a/hw/pt-graphics.c b/hw/pt-graphics.c >>>> index c6f8869..d8e789f 100644 >>>> --- a/hw/pt-graphics.c >>>> +++ b/hw/pt-graphics.c >>>> @@ -3,6 +3,7 @@ >>>> */ >>>> >>>> #include "pass-through.h" >>>> +#include "pci.h" >>>> #include "pci/header.h" >>>> #include "pci/pci.h" >>>> >>>> @@ -40,9 +41,26 @@ void intel_pch_init(PCIBus *bus) >>>> did = pt_pci_host_read(pci_dev_1f, PCI_DEVICE_ID, 2); >>>> rid = pt_pci_host_read(pci_dev_1f, PCI_REVISION, 1); >>>> >>>> - if ( vid == PCI_VENDOR_ID_INTEL ) >>>> - pci_bridge_init(bus, PCI_DEVFN(0x1f, 0), vid, did, rid, >>>> - pch_map_irq, "intel_bridge_1f"); >>>> + if (vid == PCI_VENDOR_ID_INTEL) { >>>> + PCIBridge *s = (PCIBridge *)pci_register_device(bus, >>>> "intel_bridge_1f", >>>> + sizeof(PCIBridge), PCI_DEVFN(0x1f, 0), NULL, >>>> pci_bridge_write_config); >>>> + >>>> + pci_config_set_vendor_id(s->dev.config, vid); >>>> + pci_config_set_device_id(s->dev.config, did); >>>> + >>>> + s->dev.config[PCI_COMMAND] = 0x06; // command = bus master, pci >>>> mem >>>> + s->dev.config[PCI_COMMAND + 1] = 0x00; >>>> + s->dev.config[PCI_STATUS] = 0xa0; // status = fast back-to-back, >>>> 66MHz, no error >>>> + s->dev.config[PCI_STATUS + 1] = 0x00; // status = fast devsel >>>> + s->dev.config[PCI_REVISION] = rid; >>>> + s->dev.config[PCI_CLASS_PROG] = 0x00; // programming i/f >>>> + pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_ISA); >>>> + s->dev.config[PCI_LATENCY_TIMER] = 0x10; >>>> + s->dev.config[PCI_HEADER_TYPE] = 0x81; >>>> + s->dev.config[PCI_SEC_STATUS] = 0xa0; >>>> + >>>> + s->bus = pci_register_secondary_bus(&s->dev, pch_map_irq); >>>> + } >>>> } >>>> >>>> uint32_t igd_read_opregion(struct pt_dev *pci_dev) _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxx http://lists.xen.org/xen-devel
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