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Re: [Xen-devel] [PATCH 1/2 v5] iommu/amd: Fix logic for clearing the IOMMU interrupt bits

On 6/12/2013 1:24 AM, Jan Beulich wrote:
If more entries are added to the event log during the time that event
log interrupt is disabled (in the control register),
the IOMMU hardware will generate interrupt once the the interrupt enable
bit in the control register changes from 0 to 1 and set the status
register.  Since the "iommu_interrupt_handler" code is already calling
"schedule_tasklet",  we should not need to "re-schedule" tasklet here.
I have confirmed the hardware behavior described with the hardware
designer.  This is also the same on the PPR log.
And also the same between v1 and v2 hardware? Again, I'd like to
be on the safe side, and rather do a reschedule too much than one
too little. And in any case, having your documentation made more
precise in these respects would be much appreciated.


Understand. I apologize if the AMD IOMMU specification does not describe the behavior quite clearly. Let me know if I could help clarifing any issues with the hardware designers.

Since we are modifying the IOMMU interrupt enabling/disabling, I have been doing some more testing on the IOMMU interrupt handling. I found that IOMMU MSI interrupt is currently broken, but I think this is because of some older changes. I am still tracking down the issue, and will update my findings.

Thank you,


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