Re: [Xen-devel] xen/arm: drop hip04 support

[Ian Campbell <ian.campbell@xxxxxxxxxx>]

On Tue, 2016-02-02 at 13:13 +0000, Zoltan Kiss wrote:
> This platform is no longer actively used, but it makes GICv2 development
> harder.
> 
> Signed-off-by: Zoltan Kiss <zoltan.kiss@xxxxxxxxxx>

Thanks, I appreciate the proactive removal of no-longer supported
platforms.

I was going to ask you to confirm that you were still part of Huawei while
on secondment to Linaro, but I see you have CCd that other hat of yours as
well, which is good enough for me. Hence:

Acked-by: Ian Campbell <ian.campbell@xxxxxxxxxx>

and applied.

I don't see anything obvious in the wiki / docs which would need
updating/deleting, if you know of anything please could you either update
or let us know.

Thanks,
Ian.

> ---
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 7c1bf82..12f147c 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -177,11 +177,6 @@ S:       Supported
> ÂF:   xen/arch/x86/debug.c
> ÂF:   tools/debugger/gdbsx/
> Â
> -HISILICON HIP04 SUPPORT
> -M:   Zoltan Kiss <zoltan.kiss@xxxxxxxxxx>
> -S:   Supported
> -F:   xen/arch/arm/gic-hip04.c
> -
> ÂINTEL(R) TRUSTED EXECUTION TECHNOLOGY (TXT)
> ÂM:   Gang Wei <gang.wei@xxxxxxxxx>
> ÂM:   Shane Wang <shane.wang@xxxxxxxxx>
> diff --git a/docs/misc/arm/early-printk.txt b/docs/misc/arm/early-
> printk.txt
> index 7e03955..41b528b 100644
> --- a/docs/misc/arm/early-printk.txt
> +++ b/docs/misc/arm/early-printk.txt
> @@ -37,7 +37,6 @@ the name of the machine:
> ÂÂÂ- dra7: printk with 8250 on DRA7 platform
> ÂÂÂ- exynos5250: printk with the second UART
> ÂÂÂ- fastmodel: printk on ARM Fastmodel software emulators
> -ÂÂ- hip04-d01: printk with 8250 on HiSilicon Hip-04 D01
> ÂÂÂ- juno: printk with pl011 on Juno platform
> ÂÂÂ- lager: printk with SCIF0 on Renesas R-Car H2 processors
> ÂÂÂ- midway: printk with the pl011 on Calxeda Midway processors
> diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile
> index 2f050f5..6a58a41 100644
> --- a/xen/arch/arm/Makefile
> +++ b/xen/arch/arm/Makefile
> @@ -12,7 +12,6 @@ obj-y += domctl.o
> Âobj-y += sysctl.o
> Âobj-y += domain_build.o
> Âobj-y += gic.o gic-v2.o
> -obj-$(CONFIG_ARM_32) += gic-hip04.o
> Âobj-$(CONFIG_HAS_GICV3) += gic-v3.o
> Âobj-y += io.o
> Âobj-y += irq.o
> diff --git a/xen/arch/arm/Rules.mk b/xen/arch/arm/Rules.mk
> index 4947e64..d6bbe7c 100644
> --- a/xen/arch/arm/Rules.mk
> +++ b/xen/arch/arm/Rules.mk
> @@ -42,7 +42,6 @@ EARLY_PRINTK_brcmÂÂÂÂÂÂÂÂÂÂÂ:= 8250,0xF040AB00,2
> ÂEARLY_PRINTK_dra7ÂÂÂÂÂÂÂÂÂÂÂ:= 8250,0x4806A000,2
> ÂEARLY_PRINTK_fastmodelÂÂÂÂÂÂ:= pl011,0x1c090000,115200
> ÂEARLY_PRINTK_exynos5250ÂÂÂÂÂ:= exynos4210,0x12c20000
> -EARLY_PRINTK_hip04-d01ÂÂÂÂÂÂ:= 8250,0xE4007000,2
> ÂEARLY_PRINTK_junoÂÂÂÂÂÂÂÂÂÂÂ:= pl011,0x7ff80000
> ÂEARLY_PRINTK_lagerÂÂÂÂÂÂÂÂÂÂ:= scif,0xe6e60000
> ÂEARLY_PRINTK_midwayÂÂÂÂÂÂÂÂÂ:= pl011,0xfff36000
> diff --git a/xen/arch/arm/gic-hip04.c b/xen/arch/arm/gic-hip04.c
> deleted file mode 100644
> index a42cf24..0000000
> --- a/xen/arch/arm/gic-hip04.c
> +++ /dev/null
> @@ -1,757 +0,0 @@
> -/*
> - * xen/arch/arm/gic-hip04.c
> - *
> - * Generic Interrupt Controller for HiSilicon Hip04 platform
> - * Based heavily on gic-v2.c (id
> 3bcf563fec26378f7f4cf1e2ad0d4d5b3f341919)
> - *
> - * Tim Deegan <tim@xxxxxxx>
> - * Copyright (c) 2011 Citrix Systems.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License as published by
> - * the Free Software Foundation; either version 2 of the License, or
> - * (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.ÂÂSee the
> - * GNU General Public License for more details.
> - */
> -
> -#include <xen/config.h>
> -#include <xen/lib.h>
> -#include <xen/init.h>
> -#include <xen/mm.h>
> -#include <xen/irq.h>
> -#include <xen/sched.h>
> -#include <xen/errno.h>
> -#include <xen/softirq.h>
> -#include <xen/list.h>
> -#include <xen/device_tree.h>
> -#include <xen/libfdt/libfdt.h>
> -#include <xen/sizes.h>
> -#include <asm/p2m.h>
> -#include <asm/domain.h>
> -#include <asm/platform.h>
> -#include <asm/device.h>
> -
> -#include <asm/io.h>
> -#include <asm/gic.h>
> -
> -/*
> - * LR register definitions are GIC v2 specific.
> - * Moved these definitions from header file to here
> - */
> -#define GICH_V2_LR_VIRTUAL_MASKÂÂÂÂ0x3ff
> -#define GICH_V2_LR_VIRTUAL_SHIFTÂÂÂ0
> -#define GICH_V2_LR_PHYSICAL_MASKÂÂÂ0x3ff
> -#define GICH_V2_LR_PHYSICAL_SHIFTÂÂ10
> -#define GICH_V2_LR_STATE_MASKÂÂÂÂÂÂ0x3
> -#define GICH_V2_LR_STATE_SHIFTÂÂÂÂÂ28
> -#define GICH_V2_LR_PRIORITY_SHIFTÂÂ23
> -#define GICH_V2_LR_PRIORITY_MASKÂÂÂ0x1f
> -#define GICH_V2_LR_HW_SHIFTÂÂÂÂÂÂÂÂ31
> -#define GICH_V2_LR_HW_MASKÂÂÂÂÂÂÂÂÂ0x1
> -#define GICH_V2_LR_GRP_SHIFTÂÂÂÂÂÂÂ30
> -#define GICH_V2_LR_GRP_MASKÂÂÂÂÂÂÂÂ0x1
> -#define GICH_V2_LR_MAINTENANCE_IRQ (1<<19)
> -#define GICH_V2_LR_GRP1ÂÂÂÂÂÂÂÂÂÂÂÂ(1<<30)
> -#define GICH_V2_LR_HWÂÂÂÂÂÂÂÂÂÂÂÂÂÂ(1<<31)
> -#define GICH_V2_LR_CPUID_SHIFTÂÂÂÂÂ9
> -#define GICH_V2_VTR_NRLRGSÂÂÂÂÂÂÂÂÂ0x3f
> -
> -#define GICH_V2_VMCR_PRIORITY_MASKÂÂÂ0x1f
> -#define GICH_V2_VMCR_PRIORITY_SHIFTÂÂ27
> -
> -/* Global state */
> -static struct {
> -ÂÂÂÂvoid __iomem * map_dbase; /* IO mapped Address of distributor
> registers */
> -ÂÂÂÂvoid __iomem * map_cbase[2]; /* IO mapped Address of CPU interface
> registers */
> -ÂÂÂÂvoid __iomem * map_hbase; /* IO Address of virtual interface
> registers */
> -ÂÂÂÂspinlock_t lock;
> -} gicv2;
> -
> -static struct gic_info gicv2_info;
> -
> -/* The GIC mapping of CPU interfaces does not necessarily match the
> - * logical CPU numbering. Let's use mapping as returned by the GIC
> - * itself
> - */
> -static DEFINE_PER_CPU(u16, gic_cpu_id);
> -
> -/* Maximum cpu interface per GIC */
> -#define NR_GIC_CPU_IF 16
> -
> -#define HIP04_GICD_SGI_TARGET_SHIFT 8
> -
> -#define HIP04_GICH_APRÂÂÂ0x70
> -#define HIP04_GICH_LRÂÂÂÂ0x80
> -
> -static inline void writeb_gicd(uint8_t val, unsigned int offset)
> -{
> -ÂÂÂÂwriteb_relaxed(val, gicv2.map_dbase + offset);
> -}
> -
> -static inline void writew_gicd(uint16_t val, unsigned int offset)
> -{
> -ÂÂÂÂwritew_relaxed(val, gicv2.map_dbase + offset);
> -}
> -
> -static inline void writel_gicd(uint32_t val, unsigned int offset)
> -{
> -ÂÂÂÂwritel_relaxed(val, gicv2.map_dbase + offset);
> -}
> -
> -static inline uint32_t readl_gicd(unsigned int offset)
> -{
> -ÂÂÂÂreturn readl_relaxed(gicv2.map_dbase + offset);
> -}
> -
> -static inline void writel_gicc(uint32_t val, unsigned int offset)
> -{
> -ÂÂÂÂunsigned int page = offset >> PAGE_SHIFT;
> -ÂÂÂÂoffset &= ~PAGE_MASK;
> -ÂÂÂÂwritel_relaxed(val, gicv2.map_cbase[page] + offset);
> -}
> -
> -static inline uint32_t readl_gicc(unsigned int offset)
> -{
> -ÂÂÂÂunsigned int page = offset >> PAGE_SHIFT;
> -ÂÂÂÂoffset &= ~PAGE_MASK;
> -ÂÂÂÂreturn readl_relaxed(gicv2.map_cbase[page] + offset);
> -}
> -
> -static inline void writel_gich(uint32_t val, unsigned int offset)
> -{
> -ÂÂÂÂwritel_relaxed(val, gicv2.map_hbase + offset);
> -}
> -
> -static inline uint32_t readl_gich(int unsigned offset)
> -{
> -ÂÂÂÂreturn readl_relaxed(gicv2.map_hbase + offset);
> -}
> -
> -static unsigned int hip04gic_cpu_mask(const cpumask_t *cpumask)
> -{
> -ÂÂÂÂunsigned int cpu;
> -ÂÂÂÂunsigned int mask = 0;
> -ÂÂÂÂcpumask_t possible_mask;
> -
> -ÂÂÂÂcpumask_and(&possible_mask, cpumask, &cpu_possible_map);
> -ÂÂÂÂfor_each_cpu( cpu, &possible_mask )
> -ÂÂÂÂ{
> -ÂÂÂÂÂÂÂÂASSERT(cpu < NR_GIC_CPU_IF);
> -ÂÂÂÂÂÂÂÂmask |= per_cpu(gic_cpu_id, cpu);
> -ÂÂÂÂ}
> -
> -ÂÂÂÂreturn mask;
> -}
> -
> -static void hip04gic_save_state(struct vcpu *v)
> -{
> -ÂÂÂÂint i;
> -
> -ÂÂÂÂ/* No need for spinlocks here because interrupts are disabled around
> -ÂÂÂÂÂ* this call and it only accesses struct vcpu fields that cannot be
> -ÂÂÂÂÂ* accessed simultaneously by another pCPU.
> -ÂÂÂÂÂ*/
> -ÂÂÂÂfor ( i = 0; i < gicv2_info.nr_lrs; i++ )
> -ÂÂÂÂÂÂÂÂv->arch.gic.v2.lr[i] = readl_gich(HIP04_GICH_LR + i * 4);
> -
> -ÂÂÂÂv->arch.gic.v2.apr = readl_gich(HIP04_GICH_APR);
> -ÂÂÂÂv->arch.gic.v2.vmcr = readl_gich(GICH_VMCR);
> -ÂÂÂÂ/* Disable until next VCPU scheduled */
> -ÂÂÂÂwritel_gich(0, GICH_HCR);
> -}
> -
> -static void hip04gic_restore_state(const struct vcpu *v)
> -{
> -ÂÂÂÂint i;
> -
> -ÂÂÂÂfor ( i = 0; i < gicv2_info.nr_lrs; i++ )
> -ÂÂÂÂÂÂÂÂwritel_gich(v->arch.gic.v2.lr[i], HIP04_GICH_LR + i * 4);
> -
> -ÂÂÂÂwritel_gich(v->arch.gic.v2.apr, HIP04_GICH_APR);
> -ÂÂÂÂwritel_gich(v->arch.gic.v2.vmcr, GICH_VMCR);
> -ÂÂÂÂwritel_gich(GICH_HCR_EN, GICH_HCR);
> -}
> -
> -static void hip04gic_dump_state(const struct vcpu *v)
> -{
> -ÂÂÂÂint i;
> -
> -ÂÂÂÂif ( v == current )
> -ÂÂÂÂ{
> -ÂÂÂÂÂÂÂÂfor ( i = 0; i < gicv2_info.nr_lrs; i++ )
> -ÂÂÂÂÂÂÂÂÂÂÂÂprintk("ÂÂÂHW_LR[%d]=%x\n", i,
> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂreadl_gich(HIP04_GICH_LR + i * 4));
> -ÂÂÂÂ}
> -ÂÂÂÂelse
> -ÂÂÂÂ{
> -ÂÂÂÂÂÂÂÂfor ( i = 0; i < gicv2_info.nr_lrs; i++ )
> -ÂÂÂÂÂÂÂÂÂÂÂÂprintk("ÂÂÂVCPU_LR[%d]=%x\n", i, v->arch.gic.v2.lr[i]);
> -ÂÂÂÂ}
> -}
> -
> -static void hip04gic_eoi_irq(struct irq_desc *irqd)
> -{
> -ÂÂÂÂint irq = irqd->irq;
> -ÂÂÂÂ/* Lower the priority */
> -ÂÂÂÂwritel_gicc(irq, GICC_EOIR);
> -}
> -
> -static void hip04gic_dir_irq(struct irq_desc *irqd)
> -{
> -ÂÂÂÂ/* Deactivate */
> -ÂÂÂÂwritel_gicc(irqd->irq, GICC_DIR);
> -}
> -
> -static unsigned int hip04gic_read_irq(void)
> -{
> -ÂÂÂÂreturn (readl_gicc(GICC_IAR) & GICC_IA_IRQ);
> -}
> -
> -/*
> - * needs to be called with a valid cpu_mask, ie each cpu in the mask has
> - * already called gic_cpu_init
> - */
> -static void hip04gic_set_irq_properties(struct irq_desc *desc,
> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂconst cpumask_t *cpu_mask,
> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂunsigned int priority)
> -{
> -ÂÂÂÂuint32_t cfg, actual, edgebit;
> -ÂÂÂÂunsigned int mask = hip04gic_cpu_mask(cpu_mask);
> -ÂÂÂÂunsigned int irq = desc->irq;
> -ÂÂÂÂunsigned int type = desc->arch.type;
> -
> -ÂÂÂÂASSERT(type != DT_IRQ_TYPE_INVALID);
> -ÂÂÂÂASSERT(spin_is_locked(&desc->lock));
> -
> -ÂÂÂÂspin_lock(&gicv2.lock);
> -ÂÂÂÂ/* Set edge / level */
> -ÂÂÂÂcfg = readl_gicd(GICD_ICFGR + (irq / 16) * 4);
> -ÂÂÂÂedgebit = 2u << (2 * (irq % 16));
> -ÂÂÂÂif ( type & DT_IRQ_TYPE_LEVEL_MASK )
> -ÂÂÂÂÂÂÂÂcfg &= ~edgebit;
> -ÂÂÂÂelse if ( type & DT_IRQ_TYPE_EDGE_BOTH )
> -ÂÂÂÂÂÂÂÂcfg |= edgebit;
> -ÂÂÂÂwritel_gicd(cfg, GICD_ICFGR + (irq / 16) * 4);
> -
> -ÂÂÂÂactual = readl_gicd(GICD_ICFGR + (irq / 16) * 4);
> -ÂÂÂÂif ( ( cfg & edgebit ) ^ ( actual & edgebit ) )
> -ÂÂÂÂ{
> -ÂÂÂÂÂÂÂÂprintk(XENLOG_WARNING "GIC-HIP04: WARNING: "
> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ"CPU%d: Failed to configure IRQ%u as %s-triggered. "
> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ"H/w forces to %s-triggered.\n",
> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂsmp_processor_id(), desc->irq,
> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂcfg & edgebit ? "Edge" : "Level",
> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂactual & edgebit ? "Edge" : "Level");
> -ÂÂÂÂÂÂÂÂdesc->arch.type = actual & edgebit ?
> -ÂÂÂÂÂÂÂÂÂÂÂÂDT_IRQ_TYPE_EDGE_RISING :
> -ÂÂÂÂÂÂÂÂÂÂÂÂDT_IRQ_TYPE_LEVEL_HIGH;
> -ÂÂÂÂ}
> -
> -ÂÂÂÂ/* Set target CPU mask (RAZ/WI on uniprocessor) */
> -ÂÂÂÂwritew_gicd(mask, GICD_ITARGETSR + irq * 2);
> -ÂÂÂÂ/* Set priority */
> -ÂÂÂÂwriteb_gicd(priority, GICD_IPRIORITYR + irq);
> -
> -ÂÂÂÂspin_unlock(&gicv2.lock);
> -}
> -
> -static void __init hip04gic_dist_init(void)
> -{
> -ÂÂÂÂuint32_t type;
> -ÂÂÂÂuint32_t cpumask;
> -ÂÂÂÂuint32_t gic_cpus;
> -ÂÂÂÂunsigned int nr_lines;
> -ÂÂÂÂint i;
> -
> -ÂÂÂÂcpumask = readl_gicd(GICD_ITARGETSR) & 0xffff;
> -ÂÂÂÂcpumask |= cpumask << 16;
> -
> -ÂÂÂÂ/* Disable the distributor */
> -ÂÂÂÂwritel_gicd(0, GICD_CTLR);
> -
> -ÂÂÂÂtype = readl_gicd(GICD_TYPER);
> -ÂÂÂÂnr_lines = 32 * ((type & GICD_TYPE_LINES) + 1);
> -ÂÂÂÂgic_cpus = 16;
> -ÂÂÂÂprintk("GIC-HIP04: %d lines, %d cpu%s%s (IID %8.8x).\n",
> -ÂÂÂÂÂÂÂÂÂÂÂnr_lines, gic_cpus, (gic_cpus == 1) ? "" : "s",
> -ÂÂÂÂÂÂÂÂÂÂÂ(type & GICD_TYPE_SEC) ? ", secure" : "",
> -ÂÂÂÂÂÂÂÂÂÂÂreadl_gicd(GICD_IIDR));
> -
> -ÂÂÂÂ/* Default all global IRQs to level, active low */
> -ÂÂÂÂfor ( i = 32; i < nr_lines; i += 16 )
> -ÂÂÂÂÂÂÂÂwritel_gicd(0x0, GICD_ICFGR + (i / 16) * 4);
> -
> -ÂÂÂÂ/* Route all global IRQs to this CPU */
> -ÂÂÂÂfor ( i = 32; i < nr_lines; i += 2 )
> -ÂÂÂÂÂÂÂÂwritel_gicd(cpumask, GICD_ITARGETSR + (i / 2) * 4);
> -
> -ÂÂÂÂ/* Default priority for global interrupts */
> -ÂÂÂÂfor ( i = 32; i < nr_lines; i += 4 )
> -ÂÂÂÂÂÂÂÂwritel_gicd(GIC_PRI_IRQ << 24 | GIC_PRI_IRQ << 16 |
> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂGIC_PRI_IRQ << 8 | GIC_PRI_IRQ,
> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂGICD_IPRIORITYR + (i / 4) * 4);
> -
> -ÂÂÂÂ/* Disable all global interrupts */
> -ÂÂÂÂfor ( i = 32; i < nr_lines; i += 32 )
> -ÂÂÂÂÂÂÂÂwritel_gicd(~0x0, GICD_ICENABLER + (i / 32) * 4);
> -
> -ÂÂÂÂ/* Only 1020 interrupts are supported */
> -ÂÂÂÂgicv2_info.nr_lines = min(1020U, nr_lines);
> -
> -ÂÂÂÂ/* Turn on the distributor */
> -ÂÂÂÂwritel_gicd(GICD_CTL_ENABLE, GICD_CTLR);
> -}
> -
> -static void hip04gic_cpu_init(void)
> -{
> -ÂÂÂÂint i;
> -
> -ÂÂÂÂthis_cpu(gic_cpu_id) = readl_gicd(GICD_ITARGETSR) & 0xffff;
> -
> -ÂÂÂÂ/* The first 32 interrupts (PPI and SGI) are banked per-cpu, so
> -ÂÂÂÂÂ* even though they are controlled with GICD registers, they must
> -ÂÂÂÂÂ* be set up here with the other per-cpu state. */
> -ÂÂÂÂwritel_gicd(0xffff0000, GICD_ICENABLER); /* Disable all PPI */
> -ÂÂÂÂwritel_gicd(0x0000ffff, GICD_ISENABLER); /* Enable all SGI */
> -
> -ÂÂÂÂ/* Set SGI priorities */
> -ÂÂÂÂfor ( i = 0; i < 16; i += 4 )
> -ÂÂÂÂÂÂÂÂwritel_gicd(GIC_PRI_IPI << 24 | GIC_PRI_IPI << 16 |
> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂGIC_PRI_IPI << 8 | GIC_PRI_IPI,
> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂGICD_IPRIORITYR + (i / 4) * 4);
> -
> -ÂÂÂÂ/* Set PPI priorities */
> -ÂÂÂÂfor ( i = 16; i < 32; i += 4 )
> -ÂÂÂÂÂÂÂÂwritel_gicd(GIC_PRI_IRQ << 24 | GIC_PRI_IRQ << 16 |
> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂGIC_PRI_IRQ << 8 | GIC_PRI_IRQ,
> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂGICD_IPRIORITYR + (i / 4) * 4);
> -
> -ÂÂÂÂ/* Local settings: interface controller */
> -ÂÂÂÂ/* Don't mask by priority */
> -ÂÂÂÂwritel_gicc(0xff, GICC_PMR);
> -ÂÂÂÂ/* Finest granularity of priority */
> -ÂÂÂÂwritel_gicc(0x0, GICC_BPR);
> -ÂÂÂÂ/* Turn on delivery */
> -ÂÂÂÂwritel_gicc(GICC_CTL_ENABLE|GICC_CTL_EOI, GICC_CTLR);
> -}
> -
> -static void hip04gic_cpu_disable(void)
> -{
> -ÂÂÂÂwritel_gicc(0x0, GICC_CTLR);
> -}
> -
> -static void hip04gic_hyp_init(void)
> -{
> -ÂÂÂÂuint32_t vtr;
> -ÂÂÂÂuint8_t nr_lrs;
> -
> -ÂÂÂÂvtr = readl_gich(GICH_VTR);
> -ÂÂÂÂnr_lrsÂÂ= (vtr & GICH_V2_VTR_NRLRGS) + 1;
> -ÂÂÂÂgicv2_info.nr_lrs = nr_lrs;
> -}
> -
> -static void hip04gic_hyp_disable(void)
> -{
> -ÂÂÂÂwritel_gich(0, GICH_HCR);
> -}
> -
> -static int hip04gic_secondary_cpu_init(void)
> -{
> -ÂÂÂÂspin_lock(&gicv2.lock);
> -
> -ÂÂÂÂhip04gic_cpu_init();
> -ÂÂÂÂhip04gic_hyp_init();
> -
> -ÂÂÂÂspin_unlock(&gicv2.lock);
> -
> -ÂÂÂÂreturn 0;
> -}
> -
> -static void hip04gic_send_SGI(enum gic_sgi sgi, enum gic_sgi_mode
> irqmode,
> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂconst cpumask_t *cpu_mask)
> -{
> -ÂÂÂÂunsigned int mask = 0;
> -ÂÂÂÂcpumask_t online_mask;
> -
> -ÂÂÂÂswitch ( irqmode )
> -ÂÂÂÂ{
> -ÂÂÂÂcase SGI_TARGET_OTHERS:
> -ÂÂÂÂÂÂÂÂwritel_gicd(GICD_SGI_TARGET_OTHERS | sgi, GICD_SGIR);
> -ÂÂÂÂÂÂÂÂbreak;
> -ÂÂÂÂcase SGI_TARGET_SELF:
> -ÂÂÂÂÂÂÂÂwritel_gicd(GICD_SGI_TARGET_SELF | sgi, GICD_SGIR);
> -ÂÂÂÂÂÂÂÂbreak;
> -ÂÂÂÂcase SGI_TARGET_LIST:
> -ÂÂÂÂÂÂÂÂcpumask_and(&online_mask, cpu_mask, &cpu_online_map);
> -ÂÂÂÂÂÂÂÂmask = hip04gic_cpu_mask(&online_mask);
> -ÂÂÂÂÂÂÂÂwritel_gicd(GICD_SGI_TARGET_LIST |
> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ(mask << HIP04_GICD_SGI_TARGET_SHIFT) | sgi,
> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂGICD_SGIR);
> -ÂÂÂÂÂÂÂÂbreak;
> -ÂÂÂÂdefault:
> -ÂÂÂÂÂÂÂÂBUG();
> -ÂÂÂÂ}
> -}
> -
> -/* Shut down the per-CPU GIC interface */
> -static void hip04gic_disable_interface(void)
> -{
> -ÂÂÂÂspin_lock(&gicv2.lock);
> -ÂÂÂÂhip04gic_cpu_disable();
> -ÂÂÂÂhip04gic_hyp_disable();
> -ÂÂÂÂspin_unlock(&gicv2.lock);
> -}
> -
> -static void hip04gic_update_lr(int lr, const struct pending_irq *p,
> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂunsigned int state)
> -{
> -ÂÂÂÂuint32_t lr_reg;
> -
> -ÂÂÂÂBUG_ON(lr >= gicv2_info.nr_lrs);
> -ÂÂÂÂBUG_ON(lr < 0);
> -
> -ÂÂÂÂlr_reg = (((state & GICH_V2_LR_STATE_MASK) <<
> GICH_V2_LR_STATE_SHIFT)ÂÂ|
> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂ((GIC_PRI_TO_GUEST(p->priority) &
> GICH_V2_LR_PRIORITY_MASK)
> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ<<
> GICH_V2_LR_PRIORITY_SHIFT) |
> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂ((p->irq & GICH_V2_LR_VIRTUAL_MASK) <<
> GICH_V2_LR_VIRTUAL_SHIFT));
> -
> -ÂÂÂÂif ( p->desc != NULL )
> -ÂÂÂÂÂÂÂÂlr_reg |= GICH_V2_LR_HW | ((p->desc->irq &
> GICH_V2_LR_PHYSICAL_MASK )
> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ<< GICH_V2_LR_PHYSICAL_SHIFT);
> -
> -ÂÂÂÂwritel_gich(lr_reg, HIP04_GICH_LR + lr * 4);
> -}
> -
> -static void hip04gic_clear_lr(int lr)
> -{
> -ÂÂÂÂwritel_gich(0, HIP04_GICH_LR + lr * 4);
> -}
> -
> -static void hip04gic_read_lr(int lr, struct gic_lr *lr_reg)
> -{
> -ÂÂÂÂuint32_t lrv;
> -
> -ÂÂÂÂlrvÂÂÂÂÂÂÂÂÂÂ= readl_gich(HIP04_GICH_LR + lr * 4);
> -ÂÂÂÂlr_reg->pirq = (lrv >> GICH_V2_LR_PHYSICAL_SHIFT) &
> GICH_V2_LR_PHYSICAL_MASK;
> -ÂÂÂÂlr_reg->virq = (lrv >> GICH_V2_LR_VIRTUAL_SHIFT) &
> GICH_V2_LR_VIRTUAL_MASK;
> -ÂÂÂÂlr_reg->priority = (lrv >> GICH_V2_LR_PRIORITY_SHIFT) &
> GICH_V2_LR_PRIORITY_MASK;
> -ÂÂÂÂlr_reg->stateÂÂÂÂÂ= (lrv >> GICH_V2_LR_STATE_SHIFT) &
> GICH_V2_LR_STATE_MASK;
> -ÂÂÂÂlr_reg->hw_status = (lrv >> GICH_V2_LR_HW_SHIFT) &
> GICH_V2_LR_HW_MASK;
> -ÂÂÂÂlr_reg->grpÂÂÂÂÂÂÂ= (lrv >> GICH_V2_LR_GRP_SHIFT) &
> GICH_V2_LR_GRP_MASK;
> -}
> -
> -static void hip04gic_write_lr(int lr, const struct gic_lr *lr_reg)
> -{
> -ÂÂÂÂuint32_t lrv = 0;
> -
> -ÂÂÂÂlrv = ( ((lr_reg->pirq & GICH_V2_LR_PHYSICAL_MASK) <<
> GICH_V2_LR_PHYSICAL_SHIFT) |
> -ÂÂÂÂÂÂÂÂÂÂ((lr_reg->virq & GICH_V2_LR_VIRTUAL_MASK) <<
> GICH_V2_LR_VIRTUAL_SHIFT)ÂÂÂ|
> -ÂÂÂÂÂÂÂÂÂÂ((uint32_t)(lr_reg->priority & GICH_V2_LR_PRIORITY_MASK)
> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ<< GICH_V2_LR_PRIORITY_SHIFT) |
> -ÂÂÂÂÂÂÂÂÂÂ((uint32_t)(lr_reg->state & GICH_V2_LR_STATE_MASK)
> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ<< GICH_V2_LR_STATE_SHIFT) |
> -ÂÂÂÂÂÂÂÂÂÂ((uint32_t)(lr_reg->hw_status & GICH_V2_LR_HW_MASK)
> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ<< GICH_V2_LR_HW_SHIFT)ÂÂ|
> -ÂÂÂÂÂÂÂÂÂÂ((uint32_t)(lr_reg->grp & GICH_V2_LR_GRP_MASK) <<
> GICH_V2_LR_GRP_SHIFT) );
> -
> -ÂÂÂÂwritel_gich(lrv, HIP04_GICH_LR + lr * 4);
> -}
> -
> -static void hip04gic_hcr_status(uint32_t flag, bool_t status)
> -{
> -ÂÂÂÂuint32_t hcr = readl_gich(GICH_HCR);
> -
> -ÂÂÂÂif ( status )
> -ÂÂÂÂÂÂÂÂhcr |= flag;
> -ÂÂÂÂelse
> -ÂÂÂÂÂÂÂÂhcr &= (~flag);
> -
> -ÂÂÂÂwritel_gich(hcr, GICH_HCR);
> -}
> -
> -static unsigned int hip04gic_read_vmcr_priority(void)
> -{
> -ÂÂÂreturn ((readl_gich(GICH_VMCR) >> GICH_V2_VMCR_PRIORITY_SHIFT)
> -ÂÂÂÂÂÂÂÂÂÂÂ& GICH_V2_VMCR_PRIORITY_MASK);
> -}
> -
> -static unsigned int hip04gic_read_apr(int apr_reg)
> -{
> -ÂÂÂreturn readl_gich(HIP04_GICH_APR);
> -}
> -
> -static void hip04gic_irq_enable(struct irq_desc *desc)
> -{
> -ÂÂÂÂunsigned long flags;
> -ÂÂÂÂint irq = desc->irq;
> -
> -ÂÂÂÂASSERT(spin_is_locked(&desc->lock));
> -
> -ÂÂÂÂspin_lock_irqsave(&gicv2.lock, flags);
> -ÂÂÂÂclear_bit(_IRQ_DISABLED, &desc->status);
> -ÂÂÂÂdsb(sy);
> -ÂÂÂÂ/* Enable routing */
> -ÂÂÂÂwritel_gicd((1u << (irq % 32)), GICD_ISENABLER + (irq / 32) * 4);
> -ÂÂÂÂspin_unlock_irqrestore(&gicv2.lock, flags);
> -}
> -
> -static void hip04gic_irq_disable(struct irq_desc *desc)
> -{
> -ÂÂÂÂunsigned long flags;
> -ÂÂÂÂint irq = desc->irq;
> -
> -ÂÂÂÂASSERT(spin_is_locked(&desc->lock));
> -
> -ÂÂÂÂspin_lock_irqsave(&gicv2.lock, flags);
> -ÂÂÂÂ/* Disable routing */
> -ÂÂÂÂwritel_gicd(1u << (irq % 32), GICD_ICENABLER + (irq / 32) * 4);
> -ÂÂÂÂset_bit(_IRQ_DISABLED, &desc->status);
> -ÂÂÂÂspin_unlock_irqrestore(&gicv2.lock, flags);
> -}
> -
> -static unsigned int hip04gic_irq_startup(struct irq_desc *desc)
> -{
> -ÂÂÂÂhip04gic_irq_enable(desc);
> -
> -ÂÂÂÂreturn 0;
> -}
> -
> -static void hip04gic_irq_shutdown(struct irq_desc *desc)
> -{
> -ÂÂÂÂhip04gic_irq_disable(desc);
> -}
> -
> -static void hip04gic_irq_ack(struct irq_desc *desc)
> -{
> -ÂÂÂÂ/* No ACK -- reading IAR has done this for us */
> -}
> -
> -static void hip04gic_host_irq_end(struct irq_desc *desc)
> -{
> -ÂÂÂÂ/* Lower the priority */
> -ÂÂÂÂhip04gic_eoi_irq(desc);
> -ÂÂÂÂ/* Deactivate */
> -ÂÂÂÂhip04gic_dir_irq(desc);
> -}
> -
> -static void hip04gic_guest_irq_end(struct irq_desc *desc)
> -{
> -ÂÂÂÂ/* Lower the priority of the IRQ */
> -ÂÂÂÂhip04gic_eoi_irq(desc);
> -ÂÂÂÂ/* Deactivation happens in maintenance interrupt / via GICV */
> -}
> -
> -static void hip04gic_irq_set_affinity(struct irq_desc *desc, const
> cpumask_t *cpu_mask)
> -{
> -ÂÂÂÂunsigned int mask;
> -
> -ÂÂÂÂASSERT(!cpumask_empty(cpu_mask));
> -
> -ÂÂÂÂspin_lock(&gicv2.lock);
> -
> -ÂÂÂÂmask = hip04gic_cpu_mask(cpu_mask);
> -
> -ÂÂÂÂ/* Set target CPU mask (RAZ/WI on uniprocessor) */
> -ÂÂÂÂwritew_gicd(mask, GICD_ITARGETSR + desc->irq * 2);
> -
> -ÂÂÂÂspin_unlock(&gicv2.lock);
> -}
> -
> -static int hip04gic_make_hwdom_dt_node(const struct domain *d,
> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂconst struct dt_device_node *gic,
> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂvoid *fdt)
> -{
> -ÂÂÂÂconst void *compatible;
> -ÂÂÂÂu32 len;
> -ÂÂÂÂconst __be32 *regs;
> -ÂÂÂÂint res = 0;
> -
> -ÂÂÂÂ/*
> -ÂÂÂÂÂ* Replace compatibility string with a standard one.
> -ÂÂÂÂÂ* dom0 will see a compatible GIC. This as GICC is compatible
> -ÂÂÂÂÂ* with standard one and GICD (emulated by Xen) is compatible
> -ÂÂÂÂÂ* to standard. Otherwise we should implement HIP04 GICD in
> -ÂÂÂÂÂ* the virtual GIC.
> -ÂÂÂÂÂ* This actually limit CPU number to 8 for dom0.
> -ÂÂÂÂÂ*/
> -ÂÂÂÂcompatible = DT_COMPAT_GIC_CORTEX_A15;
> -ÂÂÂÂlen = strlen((char*) compatible) + 1;
> -
> -ÂÂÂÂres = fdt_property(fdt, "compatible", compatible, len);
> -ÂÂÂÂif ( res )
> -ÂÂÂÂÂÂÂÂreturn res;
> -
> -ÂÂÂÂ/*
> -ÂÂÂÂÂ* DTB provides up to 4 regions to handle virtualization
> -ÂÂÂÂÂ* (in order GICD, GICC, GICH and GICV interfaces)
> -ÂÂÂÂÂ* however dom0 just needs GICD and GICC provided by Xen.
> -ÂÂÂÂÂ*/
> -ÂÂÂÂregs = dt_get_property(gic, "reg", &len);
> -ÂÂÂÂif ( !regs )
> -ÂÂÂÂ{
> -ÂÂÂÂÂÂÂÂdprintk(XENLOG_ERR, "Can't find reg property for the gic
> node\n");
> -ÂÂÂÂÂÂÂÂreturn -FDT_ERR_XEN(ENOENT);
> -ÂÂÂÂ}
> -
> -ÂÂÂÂlen = dt_cells_to_size(dt_n_addr_cells(gic) + dt_n_size_cells(gic));
> -ÂÂÂÂlen *= 2;
> -
> -ÂÂÂÂres = fdt_property(fdt, "reg", regs, len);
> -
> -ÂÂÂÂreturn res;
> -}
> -
> -/* XXX different for level vs edge */
> -static hw_irq_controller hip04gic_host_irq_type = {
> -ÂÂÂÂ.typenameÂÂÂÂÂ= "gic-hip04",
> -ÂÂÂÂ.startupÂÂÂÂÂÂ= hip04gic_irq_startup,
> -ÂÂÂÂ.shutdownÂÂÂÂÂ= hip04gic_irq_shutdown,
> -ÂÂÂÂ.enableÂÂÂÂÂÂÂ= hip04gic_irq_enable,
> -ÂÂÂÂ.disableÂÂÂÂÂÂ= hip04gic_irq_disable,
> -ÂÂÂÂ.ackÂÂÂÂÂÂÂÂÂÂ= hip04gic_irq_ack,
> -ÂÂÂÂ.endÂÂÂÂÂÂÂÂÂÂ= hip04gic_host_irq_end,
> -ÂÂÂÂ.set_affinity = hip04gic_irq_set_affinity,
> -};
> -
> -static hw_irq_controller hip04gic_guest_irq_type = {
> -ÂÂÂÂ.typenameÂÂÂÂÂ= "gic-hip04",
> -ÂÂÂÂ.startupÂÂÂÂÂÂ= hip04gic_irq_startup,
> -ÂÂÂÂ.shutdownÂÂÂÂÂ= hip04gic_irq_shutdown,
> -ÂÂÂÂ.enableÂÂÂÂÂÂÂ= hip04gic_irq_enable,
> -ÂÂÂÂ.disableÂÂÂÂÂÂ= hip04gic_irq_disable,
> -ÂÂÂÂ.ackÂÂÂÂÂÂÂÂÂÂ= hip04gic_irq_ack,
> -ÂÂÂÂ.endÂÂÂÂÂÂÂÂÂÂ= hip04gic_guest_irq_end,
> -ÂÂÂÂ.set_affinity = hip04gic_irq_set_affinity,
> -};
> -
> -static int __init hip04gic_init(void)
> -{
> -ÂÂÂÂint res;
> -ÂÂÂÂpaddr_t hbase, dbase, cbase, csize, vbase;
> -ÂÂÂÂconst struct dt_device_node *node = gicv2_info.node;
> -
> -ÂÂÂÂres = dt_device_get_address(node, 0, &dbase, NULL);
> -ÂÂÂÂif ( res )
> -ÂÂÂÂÂÂÂÂpanic("GIC-HIP04: Cannot find a valid address for the
> distributor");
> -
> -ÂÂÂÂres = dt_device_get_address(node, 1, &cbase, &csize);
> -ÂÂÂÂif ( res )
> -ÂÂÂÂÂÂÂÂpanic("GIC-HIP04: Cannot find a valid address for the CPU");
> -
> -ÂÂÂÂres = dt_device_get_address(node, 2, &hbase, NULL);
> -ÂÂÂÂif ( res )
> -ÂÂÂÂÂÂÂÂpanic("GIC-HIP04: Cannot find a valid address for the
> hypervisor");
> -
> -ÂÂÂÂres = dt_device_get_address(node, 3, &vbase, NULL);
> -ÂÂÂÂif ( res )
> -ÂÂÂÂÂÂÂÂpanic("GIC-HIP04: Cannot find a valid address for the virtual
> CPU");
> -
> -ÂÂÂÂres = platform_get_irq(node, 0);
> -ÂÂÂÂif ( res < 0 )
> -ÂÂÂÂÂÂÂÂpanic("GIC-HIP04: Cannot find the maintenance IRQ");
> -ÂÂÂÂgicv2_info.maintenance_irq = res;
> -
> -ÂÂÂÂ/* TODO: Add check on distributor, cpu size */
> -
> -ÂÂÂÂprintk("GIC-HIP04 initialization:\n"
> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂ"ÂÂÂÂÂÂÂÂgic_dist_addr=%"PRIpaddr"\n"
> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂ"ÂÂÂÂÂÂÂÂgic_cpu_addr=%"PRIpaddr"\n"
> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂ"ÂÂÂÂÂÂÂÂgic_hyp_addr=%"PRIpaddr"\n"
> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂ"ÂÂÂÂÂÂÂÂgic_vcpu_addr=%"PRIpaddr"\n"
> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂ"ÂÂÂÂÂÂÂÂgic_maintenance_irq=%u\n",
> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂdbase, cbase, hbase, vbase,
> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂgicv2_info.maintenance_irq);
> -
> -ÂÂÂÂif ( (dbase & ~PAGE_MASK) || (cbase & ~PAGE_MASK) ||
> -ÂÂÂÂÂÂÂÂÂ(hbase & ~PAGE_MASK) || (vbase & ~PAGE_MASK) )
> -ÂÂÂÂÂÂÂÂpanic("GIC-HIP04 interfaces not page aligned");
> -
> -ÂÂÂÂgicv2.map_dbase = ioremap_nocache(dbase, PAGE_SIZE);
> -ÂÂÂÂif ( !gicv2.map_dbase )
> -ÂÂÂÂÂÂÂÂpanic("GIC-HIP04: Failed to ioremap for GIC distributor\n");
> -
> -ÂÂÂÂgicv2.map_cbase[0] = ioremap_nocache(cbase, PAGE_SIZE);
> -ÂÂÂÂgicv2.map_cbase[1] = ioremap_nocache(cbase + PAGE_SIZE, PAGE_SIZE);
> -
> -ÂÂÂÂif ( !gicv2.map_cbase[0] || !gicv2.map_cbase[1] )
> -ÂÂÂÂÂÂÂÂpanic("GIC-HIP04: Failed to ioremap for GIC CPU interface\n");
> -
> -ÂÂÂÂgicv2.map_hbase = ioremap_nocache(hbase, PAGE_SIZE);
> -ÂÂÂÂif ( !gicv2.map_hbase )
> -ÂÂÂÂÂÂÂÂpanic("GIC-HIP04: Failed to ioremap for GIC Virtual
> interface\n");
> -
> -ÂÂÂÂvgic_v2_setup_hw(dbase, cbase, csize, vbase, 0);
> -
> -ÂÂÂÂ/* Global settings: interrupt distributor */
> -ÂÂÂÂspin_lock_init(&gicv2.lock);
> -ÂÂÂÂspin_lock(&gicv2.lock);
> -
> -ÂÂÂÂhip04gic_dist_init();
> -ÂÂÂÂhip04gic_cpu_init();
> -ÂÂÂÂhip04gic_hyp_init();
> -
> -ÂÂÂÂspin_unlock(&gicv2.lock);
> -
> -ÂÂÂÂreturn 0;
> -}
> -
> -const static struct gic_hw_operations hip04gic_ops = {
> -ÂÂÂÂ.infoÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ= &gicv2_info,
> -ÂÂÂÂ.initÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ= hip04gic_init,
> -ÂÂÂÂ.secondary_initÂÂÂÂÂÂ= hip04gic_secondary_cpu_init,
> -ÂÂÂÂ.save_stateÂÂÂÂÂÂÂÂÂÂ= hip04gic_save_state,
> -ÂÂÂÂ.restore_stateÂÂÂÂÂÂÂ= hip04gic_restore_state,
> -ÂÂÂÂ.dump_stateÂÂÂÂÂÂÂÂÂÂ= hip04gic_dump_state,
> -ÂÂÂÂ.gic_host_irq_typeÂÂÂ= &hip04gic_host_irq_type,
> -ÂÂÂÂ.gic_guest_irq_typeÂÂ= &hip04gic_guest_irq_type,
> -ÂÂÂÂ.eoi_irqÂÂÂÂÂÂÂÂÂÂÂÂÂ= hip04gic_eoi_irq,
> -ÂÂÂÂ.deactivate_irqÂÂÂÂÂÂ= hip04gic_dir_irq,
> -ÂÂÂÂ.read_irqÂÂÂÂÂÂÂÂÂÂÂÂ= hip04gic_read_irq,
> -ÂÂÂÂ.set_irq_propertiesÂÂ= hip04gic_set_irq_properties,
> -ÂÂÂÂ.send_SGIÂÂÂÂÂÂÂÂÂÂÂÂ= hip04gic_send_SGI,
> -ÂÂÂÂ.disable_interfaceÂÂÂ= hip04gic_disable_interface,
> -ÂÂÂÂ.update_lrÂÂÂÂÂÂÂÂÂÂÂ= hip04gic_update_lr,
> -ÂÂÂÂ.update_hcr_statusÂÂÂ= hip04gic_hcr_status,
> -ÂÂÂÂ.clear_lrÂÂÂÂÂÂÂÂÂÂÂÂ= hip04gic_clear_lr,
> -ÂÂÂÂ.read_lrÂÂÂÂÂÂÂÂÂÂÂÂÂ= hip04gic_read_lr,
> -ÂÂÂÂ.write_lrÂÂÂÂÂÂÂÂÂÂÂÂ= hip04gic_write_lr,
> -ÂÂÂÂ.read_vmcr_priorityÂÂ= hip04gic_read_vmcr_priority,
> -ÂÂÂÂ.read_aprÂÂÂÂÂÂÂÂÂÂÂÂ= hip04gic_read_apr,
> -ÂÂÂÂ.make_hwdom_dt_nodeÂÂ= hip04gic_make_hwdom_dt_node,
> -};
> -
> -/* Set up the GIC */
> -static int __init hip04gic_preinit(struct dt_device_node *node,
> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂconst void *data)
> -{
> -ÂÂÂÂgicv2_info.hw_version = GIC_V2;
> -ÂÂÂÂgicv2_info.node = node;
> -ÂÂÂÂregister_gic_ops(&hip04gic_ops);
> -ÂÂÂÂdt_irq_xlate = gic_irq_xlate;
> -
> -ÂÂÂÂreturn 0;
> -}
> -
> -static const struct dt_device_match hip04gic_dt_match[] __initconst =
> -{
> -ÂÂÂÂDT_MATCH_COMPATIBLE("hisilicon,hip04-intc"),
> -ÂÂÂÂ{ /* sentinel */ },
> -};
> -
> -DT_DEVICE_START(hip04gic, "GIC-HIP04", DEVICE_GIC)
> -ÂÂÂÂÂÂÂÂ.dt_match = hip04gic_dt_match,
> -ÂÂÂÂÂÂÂÂ.init = hip04gic_preinit,
> -DT_DEVICE_END
> -
> -/*
> - * Local variables:
> - * mode: C
> - * c-file-style: "BSD"
> - * c-basic-offset: 4
> - * indent-tabs-mode: nil
> - * End:
> - */
> 
> _______________________________________________
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