Re: [Xen-devel] Future support of 5-level paging in Xen

[Andrew Cooper <andrew.cooper3@xxxxxxxxxx>]

On 08/12/16 16:46, Juergen Gross wrote:
> The first round of (very preliminary) patches for supporting the new
> 5-level paging of future Intel x86 processors [1] has been posted to
> lkml:
>
> https://lkml.org/lkml/2016/12/8/378
>
> An explicit note has been added: "CONFIG_XEN is broken." and
> "I would appreciate help with the code."
>
> I think we should start a discussion what we want to do in future:
>
> - are we going to support 5-level paging for PV guests?
> - do we limit 5-level paging to PVH and HVM?

The 64bit PV ABI has 16TB of virtual address space just above the upper
48-canonical boundary.

Were Xen to support 5-level PV guests, we'd either leave the PV guest
kernel with exactly the same amount of higher half space as it currently
has, or we'd have to recompile Xen as properly position-independent and
use a different virtual range in different paging mode.

Another pain point is the quantity of virtual address space handed away
in the ABI.  We currently had 97% of the virtual address space away to
64bit PV guests, and frankly this is too much.  This is the wrong way
around when Xen has more management to do than the guest.  If we were to
go along the 5-level PV guests route, I will insist that there is a
rather more even split of virtual address space baked into the ABI.

However, a big question is whether any of this effort is worth doing, in
the light of PVH.

~Andrew

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