[Xen-devel] [PATCH v9 02/38] x86/mm/pat: Set write-protect cache mode for full PAT support

[Tom Lendacky <thomas.lendacky@xxxxxxx>]

For processors that support PAT, set the write-protect cache mode
(_PAGE_CACHE_MODE_WP) entry to the actual write-protect value (x05).

Acked-by: Borislav Petkov <bp@xxxxxxx>
Signed-off-by: Tom Lendacky <thomas.lendacky@xxxxxxx>
---
 arch/x86/mm/pat.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/x86/mm/pat.c b/arch/x86/mm/pat.c
index 4597950..88990ab 100644
--- a/arch/x86/mm/pat.c
+++ b/arch/x86/mm/pat.c
@@ -293,7 +293,7 @@ void init_cache_modes(void)
  * pat_init - Initialize PAT MSR and PAT table
  *
  * This function initializes PAT MSR and PAT table with an OS-defined value
- * to enable additional cache attributes, WC and WT.
+ * to enable additional cache attributes, WC, WT and WP.
  *
  * This function must be called on all CPUs using the specific sequence of
  * operations defined in Intel SDM. mtrr_rendezvous_handler() provides this
@@ -352,7 +352,7 @@ void pat_init(void)
                 *      010    2    UC-: _PAGE_CACHE_MODE_UC_MINUS
                 *      011    3    UC : _PAGE_CACHE_MODE_UC
                 *      100    4    WB : Reserved
-                *      101    5    WC : Reserved
+                *      101    5    WP : _PAGE_CACHE_MODE_WP
                 *      110    6    UC-: Reserved
                 *      111    7    WT : _PAGE_CACHE_MODE_WT
                 *
@@ -360,7 +360,7 @@ void pat_init(void)
                 * corresponding types in the presence of PAT errata.
                 */
                pat = PAT(0, WB) | PAT(1, WC) | PAT(2, UC_MINUS) | PAT(3, UC) |
-                     PAT(4, WB) | PAT(5, WC) | PAT(6, UC_MINUS) | PAT(7, WT);
+                     PAT(4, WB) | PAT(5, WP) | PAT(6, UC_MINUS) | PAT(7, WT);
        }
 
        if (!boot_cpu_done) {


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