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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH] x86/cpu: Support a new cpu vendor, which is Shanghai. Shanghai cpu defines two msr registers to enable Random Number Generator and Advanced Cryprography Engine.The cpu supports iommu, which is designed according to Intel's specification.
From: FionaLi <FionaLi@xxxxxxxxxxx>
Signed-off-by: Fiona Li<fionali@xxxxxxxxxxx>
---
xen/arch/x86/cpu/Makefile | 1 +
xen/arch/x86/cpu/common.c | 1 +
xen/arch/x86/cpu/shanghai.c | 61 +++++++++++++++++++++++++++++++++++++++
xen/include/asm-x86/iommu.h | 2 ++
xen/include/asm-x86/msr-index.h | 4 +++
xen/include/asm-x86/setup.h | 1 +
xen/include/asm-x86/x86-vendors.h | 3 +-
7 files changed, 72 insertions(+), 1 deletion(-)
create mode 100644 xen/arch/x86/cpu/shanghai.c
diff --git a/xen/arch/x86/cpu/Makefile b/xen/arch/x86/cpu/Makefile
index 74f23ae..8fcffdd 100644
--- a/xen/arch/x86/cpu/Makefile
+++ b/xen/arch/x86/cpu/Makefile
@@ -5,6 +5,7 @@ obj-y += amd.o
obj-y += centaur.o
obj-y += common.o
obj-y += intel.o
+obj-y += shanghai.o
obj-y += intel_cacheinfo.o
obj-y += mwait-idle.o
obj-y += vpmu.o vpmu_amd.o vpmu_intel.o
diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
index 0a452ae..02863c9 100644
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -709,6 +709,7 @@ void __init early_cpu_init(void)
intel_cpu_init();
amd_init_cpu();
centaur_init_cpu();
+ shanghai_init_cpu();
early_cpu_detect();
}
diff --git a/xen/arch/x86/cpu/shanghai.c b/xen/arch/x86/cpu/shanghai.c
new file mode 100644
index 0000000..7910f03
--- /dev/null
+++ b/xen/arch/x86/cpu/shanghai.c
@@ -0,0 +1,61 @@
+#include <xen/lib.h>
+#include <xen/init.h>
+#include <xen/bitops.h>
+#include <asm/processor.h>
+#include <asm/msr.h>
+#include <asm/e820.h>
+#include "cpu.h"
+
+#define ACE_PRESENT(x) ((x)&(1U<<6))
+#define ACE_ENABLED(x) ((x)&(1U<<7))
+#define ACE_FCR (1U << 28) /* MSR_ZX_ACE Advanced
Cryprography Engine */
+
+#define RNG_PRESENT(x) ((x)&(1U<<6))
+#define RNG_ENABLED(x) ((x)&(1U<<7))
+#define RNG_ENABLE (1U << 6) /* MSR_ZX_RNG Random Number Generator */
+
+
+
+static void init_shanghai(struct cpuinfo_x86 *c)
+{
+ uint64_t msr_ace,msr_rng;
+ /* Test for Shanghai Extended CPUID information */
+ if (cpuid_eax(0xC0000000) >= 0xC0000001) {
+ /*Get Shanghai Extended function number */
+ u32 extented_feature_flags = cpuid_edx(0xC0000001);
+
+ /* enable ACE,if support ACE unit */
+ if(ACE_PRESENT(extented_feature_flags) &&
!ACE_ENABLED(extented_feature_flags)) {
+ rdmsrl(MSR_ZX_ACE, msr_ace);
+ /* enable ACE */
+ wrmsrl(MSR_ZX_ACE, (msr_ace | ACE_FCR));
+ printk(KERN_INFO "CPU: Enabled ACE h/w crypto\n");
+ }
+ /* enable RNG,if support RNG unit */
+ if (RNG_PRESENT(extented_feature_flags) &&
!RNG_ENABLED(extented_feature_flags)) {
+ rdmsrl(MSR_ZX_RNG, msr_rng);
+ /* enable RNG */
+ wrmsrl(MSR_ZX_RNG, msr_rng | RNG_ENABLE);
+ printk(KERN_INFO "CPU: Enabled h/w RNG\n");
+ }
+ }
+
+ if (c->x86 == 0x6 && c->x86_model >= 0xf) {
+ c->x86_cache_alignment = c->x86_clflush_size * 2;
+ __set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
+ }
+ get_model_name(c);
+ display_cacheinfo(c);
+}
+
+static const struct cpu_dev shanghai_cpu_dev = {
+ .c_vendor = "Shanghai",
+ .c_ident = { " Shanghai " },
+ .c_init = init_shanghai,
+};
+
+int __init shanghai_init_cpu(void)
+{
+ cpu_devs[X86_VENDOR_SHANGHAI] = &shanghai_cpu_dev;
+ return 0;
+}
diff --git a/xen/include/asm-x86/iommu.h b/xen/include/asm-x86/iommu.h
index 14ad048..c125da6 100644
--- a/xen/include/asm-x86/iommu.h
+++ b/xen/include/asm-x86/iommu.h
@@ -53,6 +53,7 @@ static inline const struct iommu_ops *iommu_get_ops(void)
{
switch ( boot_cpu_data.x86_vendor )
{
+ case X86_VENDOR_SHANGHAI:
case X86_VENDOR_INTEL:
return &intel_iommu_ops;
case X86_VENDOR_AMD:
@@ -68,6 +69,7 @@ static inline int iommu_hardware_setup(void)
{
switch ( boot_cpu_data.x86_vendor )
{
+ case X86_VENDOR_SHANGHAI:
case X86_VENDOR_INTEL:
return intel_vtd_setup();
case X86_VENDOR_AMD:
diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index 23ad743..f2ce71a 100644
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -293,6 +293,10 @@
#define MSR_TMTA_LRTI_READOUT 0x80868018
#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
+/* Shanghai ZhaoXin defined MSRs*/
+#define MSR_ZX_ACE 0x00001107
+#define MSR_ZX_RNG 0x0000110b
+
/* Intel defined MSRs. */
#define MSR_IA32_P5_MC_ADDR 0x00000000
#define MSR_IA32_P5_MC_TYPE 0x00000001
diff --git a/xen/include/asm-x86/setup.h b/xen/include/asm-x86/setup.h
index 19232af..827daf8 100644
--- a/xen/include/asm-x86/setup.h
+++ b/xen/include/asm-x86/setup.h
@@ -22,6 +22,7 @@ int amd_init_cpu(void);
int cyrix_init_cpu(void);
int nsc_init_cpu(void);
int centaur_init_cpu(void);
+int shanghai_init_cpu(void);
int transmeta_init_cpu(void);
void set_nr_cpu_ids(unsigned int max_cpus);
diff --git a/xen/include/asm-x86/x86-vendors.h
b/xen/include/asm-x86/x86-vendors.h
index cae5507..c53d0b9 100644
--- a/xen/include/asm-x86/x86-vendors.h
+++ b/xen/include/asm-x86/x86-vendors.h
@@ -7,7 +7,8 @@
#define X86_VENDOR_INTEL 0
#define X86_VENDOR_AMD 1
#define X86_VENDOR_CENTAUR 2
-#define X86_VENDOR_NUM 3
+#define X86_VENDOR_SHANGHAI 3
+#define X86_VENDOR_NUM 4
#define X86_VENDOR_UNKNOWN 0xff
#endif /* __XEN_X86_VENDORS_H__ */
--
2.7.4
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