[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [Xen-devel] [PATCH] x86/cpu: Support a new cpu vendor, which is Shanghai. Shanghai cpu defines two msr registers to enable Random Number Generator and Advanced Cryprography Engine.The cpu supports iommu, which is designed according to Intel's specification.
On Fri, Mar 23, 2018 at 07:28:56PM +0800, Fionali wrote: > From: FionaLi <FionaLi@xxxxxxxxxxx> > > Signed-off-by: Fiona Li<fionali@xxxxxxxxxxx> > --- > xen/arch/x86/cpu/Makefile | 1 + > xen/arch/x86/cpu/common.c | 1 + > xen/arch/x86/cpu/shanghai.c | 61 > +++++++++++++++++++++++++++++++++++++++ > xen/include/asm-x86/iommu.h | 2 ++ > xen/include/asm-x86/msr-index.h | 4 +++ > xen/include/asm-x86/setup.h | 1 + > xen/include/asm-x86/x86-vendors.h | 3 +- > 7 files changed, 72 insertions(+), 1 deletion(-) > create mode 100644 xen/arch/x86/cpu/shanghai.c > > diff --git a/xen/arch/x86/cpu/Makefile b/xen/arch/x86/cpu/Makefile > index 74f23ae..8fcffdd 100644 > --- a/xen/arch/x86/cpu/Makefile > +++ b/xen/arch/x86/cpu/Makefile > @@ -5,6 +5,7 @@ obj-y += amd.o > obj-y += centaur.o > obj-y += common.o > obj-y += intel.o > +obj-y += shanghai.o > obj-y += intel_cacheinfo.o > obj-y += mwait-idle.o > obj-y += vpmu.o vpmu_amd.o vpmu_intel.o > diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c > index 0a452ae..02863c9 100644 > --- a/xen/arch/x86/cpu/common.c > +++ b/xen/arch/x86/cpu/common.c > @@ -709,6 +709,7 @@ void __init early_cpu_init(void) > intel_cpu_init(); > amd_init_cpu(); > centaur_init_cpu(); > + shanghai_init_cpu(); > early_cpu_detect(); > } > > diff --git a/xen/arch/x86/cpu/shanghai.c b/xen/arch/x86/cpu/shanghai.c > new file mode 100644 > index 0000000..7910f03 > --- /dev/null > +++ b/xen/arch/x86/cpu/shanghai.c > @@ -0,0 +1,61 @@ > +#include <xen/lib.h> > +#include <xen/init.h> > +#include <xen/bitops.h> > +#include <asm/processor.h> > +#include <asm/msr.h> > +#include <asm/e820.h> Use the following order please: #include <xen/bitops.h> #include <xen/init.h> #include <xen/lib.h> #include <asm/e820.h> #include <asm/msr.h> #include <asm/processor.h> > +#include "cpu.h" > + > +#define ACE_PRESENT(x) ((x)&(1U<<6)) Please add spaces around "&" and "<<". > +#define ACE_ENABLED(x) ((x)&(1U<<7)) > +#define ACE_FCR (1U << 28) /* MSR_ZX_ACE Advanced > Cryprography Engine */ > + > +#define RNG_PRESENT(x) ((x)&(1U<<6)) > +#define RNG_ENABLED(x) ((x)&(1U<<7)) > +#define RNG_ENABLE (1U << 6) /* MSR_ZX_RNG Random Number Generator */ > + > + > + > +static void init_shanghai(struct cpuinfo_x86 *c) > +{ > + uint64_t msr_ace,msr_rng; Add a blank line here. > + /* Test for Shanghai Extended CPUID information */ > + if (cpuid_eax(0xC0000000) >= 0xC0000001) { Coding style. Should be if ( XXXX ) { Please fix all instances. > + /*Get Shanghai Extended function number */ > + u32 extented_feature_flags = cpuid_edx(0xC0000001); > + > + /* enable ACE,if support ACE unit */ > + if(ACE_PRESENT(extented_feature_flags) && > !ACE_ENABLED(extented_feature_flags)) { > + rdmsrl(MSR_ZX_ACE, msr_ace); > + /* enable ACE */ > + wrmsrl(MSR_ZX_ACE, (msr_ace | ACE_FCR)); > + printk(KERN_INFO "CPU: Enabled ACE h/w crypto\n"); Drop KERN_INFO please. > + } Blank line here please. > + /* enable RNG,if support RNG unit */ > + if (RNG_PRESENT(extented_feature_flags) && > !RNG_ENABLED(extented_feature_flags)) { > + rdmsrl(MSR_ZX_RNG, msr_rng); > + /* enable RNG */ > + wrmsrl(MSR_ZX_RNG, msr_rng | RNG_ENABLE); > + printk(KERN_INFO "CPU: Enabled h/w RNG\n"); > + } > + } > + > + if (c->x86 == 0x6 && c->x86_model >= 0xf) { > + c->x86_cache_alignment = c->x86_clflush_size * 2; > + __set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability); > + } Blank line. > + get_model_name(c); > + display_cacheinfo(c); > +} Wei. _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxxxxxxxxx https://lists.xenproject.org/mailman/listinfo/xen-devel
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