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Re: [Xen-devel] [PATCH 5/6] x86/HVM: prefill cache with PDPTEs when possible

>>> On 19.07.18 at 21:07, <andrew.cooper3@xxxxxxxxxx> wrote:
> Oh - I'd not looked in that much detail at your algorithm.  As a first
> gut feel, tagging by level doesn't sound as if it will interact
> correctly with linear pagetables.
> Both the Intel and AMD ORM's maintain paging structure caches so I'd
> expect that a linear pagetable entry would be served from that cache
> rather than being read twice from RAM.

Is there anywhere enough detail about the actual implementation of
the paging structure caches? I could imagine them being per level. It
wouldn't be very difficult to switch to a tristate here (normal data,
page table, and PAE L3).


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