Re: [Xen-devel] Interrupt injection with ISR set on Intel hardware

[Roger Pau Monné <roger.pau@xxxxxxxxxx>]

On Wed, Dec 12, 2018 at 11:48:52AM +0000, Tian, Kevin wrote:
> > From: Roger Pau Monné [mailto:roger.pau@xxxxxxxxxx]
> > Sent: Wednesday, December 12, 2018 7:25 PM
> > 
> > On Wed, Dec 12, 2018 at 10:36:44AM +0000, Tian, Kevin wrote:
> > > > From: Roger Pau Monné [mailto:roger.pau@xxxxxxxxxx]
> > > > Sent: Monday, October 15, 2018 6:30 PM
> > > > (XEN)   [22642] POWER    TYPE 4
> > > > (XEN)   [22643] IDLE     PPR 0x00000020
> > > > (XEN)                    IRR
> > > >
> > 00000000000000000000000000000000000000000000000000000000000000
> > > > 00
> > > > (XEN)                    ISR
> > > >
> > 00000000020000000000000000000000000000000000000000000000000000
> > > > 00
> > > > (XEN)   [22644] WAKE     PPR 0x00000020
> > > > (XEN)                    IRR
> > > >
> > 00000000020000000000000000000000000000000000000000000000000000
> > > > 00
> > > > (XEN)                    ISR
> > > >
> > 00000000020000000000000000000000000000000000000000000000000000
> > > > 00
> > >
> > > looks pending IRR (0x21) doesn't always trigger a spurious interrupt?
> > 
> > Yes, that's correct. Having a pending IRR and going idle doesn't
> > always trigger the spurious interrupt re-injection.
> > 
> > > is it a fixed pattern after how many rounds of Cstate enter/exit with
> > > pending IRR(0x21) then you see assertion happened (in this example
> > > it happens at 3rd time)?
> > 
> > It's not a fixed pattern, here's another trace with IRR(0x21) being
> > pending just once during the Cstate transitions:
> 
> did you observe a case where such asset may occur when IRR(0x21)
> is cleared but ISR (0x21) is set?

No, I've always seen both ISR and IRR set when the interrupt injection
happens. This of course doesn't mean it's not possible, but I have not
seen any trace with ISR(0x21) set and IRR(0x21) clear.

Thanks, Roger.

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