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Re: [Xen-devel] wall clock drift on Coffee Lake / C24x mainboard (HPET broken?), best practices



On 19.11.2019 10:29, Jan Beulich wrote:
On 18.11.2019 20:35, Andreas Kinzler wrote:
On 15.11.2019 12:01, Andreas Kinzler wrote:
On 14.11.2019 12:29, Jan Beulich wrote:
On 14.11.2019 00:10, Andreas Kinzler wrote:
I came across the following: https://lkml.org/lkml/2019/8/29/536
Could that be the reason for the problem mentioned below? Xen is using
HPET as clocksource on the platform/mainboard. Is there an (easy) way to
verify if Xen uses PC10?
Hence I can only suggest that you try again with limited or no
use of C states, to at least get a hint as to a possible
I changed the BIOS setting to a limit of PC7 and it is now running. I
have to wait for the result. Thanks.

Previously the drift after 4 days uptime was 60 sec. Now after 4 days
uptime drift is 9 sec. So setting the package c-state limit to PC7 was a
success.

9s still seems quite a lot to me, but yes, it's an improvement.

It seems it is even better than some other platforms now. Some snapshot measurements from running systems:
Xeon E3-1230v5 (Skylake): drift of 4 sec per day (23.999MHz HPET)
Xeon E3-1240v6 (Kaby Lake): drift of 1.9 sec per day (23.999MHz HPET)
Xeon E3-1240v5 (Skylake): drift of 4.85 sec per day (23.999MHz HPET)
Xeon E5-1620v4 (Broadwell): drift of 2.7 sec per day (14.318MHz HPET)

All these values are not great, but it is OK for me.

Now would you be up to checking whether, rather than via BIOS
settings (which not all BIOSes may offer) the same can be
achieved by using Xen's command line option "max_cstate="?
Also did you check whether further limiting C state use would

I cannot try on production machines. I may have a slot on lab machines but I cannot promise.

> further improve the situation? And did you possibly also check
> whether telling Xen not to use the HPET would make a difference?

Which other clocksource do you prefer? Is Xen tested (field-proven) on that other clocksource?

Regards Andreas

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