Re: [PATCH 1/2] x86/intel: insert Ice Lake X (server) model numbers

[Jan Beulich <jbeulich@xxxxxxxx>]

On 14.10.2020 18:42, Igor Druzhinin wrote:
> On 14/10/2020 16:47, Jan Beulich wrote:
>> On 13.10.2020 05:02, Igor Druzhinin wrote:
>>> LBR, C-state MSRs and if_pschange_mc erratum applicability should correspond
>>> to Ice Lake desktop according to External Design Specification vol.2.
>>
>> Could you tell me where this is publicly available? Even after spending
>> quite a bit of time on searching for it, I can't seem to be able to
>> find it. And the SDM doesn't have enough information (yet).
> 
> True that SDM doesn't have this data. As I mentioned that data is taken from
> External Design Specification for Ice Lake server which is accessed using 
> Intel
> account. I'm not completely sure it is right to make changes in open source
> project like Linux or Xen based on information which is not publicly available
> yet. But Intel is frequently doing this with Linux : even my second patch uses
> data taken from one of these documents and was committed by Intel to Linux 
> first.
> 
> Do we need the information publicly available to commit these changes as well?

Not necessarily, but it means this patch needs to be acked by someone
having access to the doc, which hence isn't me. Given the last SDM
update was in May, I'm expecting a refresh any day now. Iirc updates
where frequently done on a roughly quarterly basis.

> If not, we can run with these changes in our patchqueue until it gets out 
> properly.

Well, I'm all for having such changes upstream as early as possible.

Jan