Re: Need guidance to support reading GICR_TYPER (64 bit register) on Aarch32_v8r

[Julien Grall <julien@xxxxxxx>]

Hi Ayan,

On 13/10/2022 17:05, Ayan Kumar Halder wrote:
> On 13/10/2022 16:38, Julien Grall wrote:
> > Hi,
> Hi Julien,
> > On 13/10/2022 16:13, Ayan Kumar Halder wrote:
> > > On 13/10/2022 15:47, Julien Grall wrote:
> > > > > .Thus, the guest need to invoke sys_read32() twice (GICR_TYPER and 
> > > > > GICR_TYPER+4).
> > > > I don't understand how you came to this conclusion with what you wrote. 
> > > Sorry for confusion. I was trying to explain that the code does not 
> > > handle 32 bit access of GICR_TYPER on arm32.
> > >
> > > > If we had implemented vreg_reg64_extract(), then Zephyr would still 
> > > > need to issue two 32-bit read because Xen doesn't emulate 'ldrd'.
> > > Yes. So what we need here is not the implementation of 
> > > vreg_reg64_extract() for GICR_TYPER.
> > Why not? Your GICR_TYPER is a 64-bit and the helper is the right way 
> > to hide whether the low/high 32-bit are accessed.
> When Zephyr issues 32 bit reads for GICR_TYPER for GICR_TYPER + 4, it 
> traps to Xen two times.
> So, my understanding is that Xen needs to read two 32 bit values.
>
> We can modify the vreg_reg64_extract() so that it can return the lower 
> 32 bits in one case and upper 32 bits in the second case.
> Is this what you are suggesting ?
Well... The helper is already doing that. It was introduced to support 
32-bit guest using GICv3 on 64-bit Xen.
Cheers,

--
Julien Grall