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RE: [PATCH 3/4] xen/arm: pl011: Use correct accessors
- To: Michal Orzel <michal.orzel@xxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- From: Henry Wang <Henry.Wang@xxxxxxx>
- Date: Tue, 13 Jun 2023 02:59:40 +0000
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- Cc: Stefano Stabellini <sstabellini@xxxxxxxxxx>, Julien Grall <julien@xxxxxxx>, Bertrand Marquis <Bertrand.Marquis@xxxxxxx>, Volodymyr Babchuk <Volodymyr_Babchuk@xxxxxxxx>
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- Thread-topic: [PATCH 3/4] xen/arm: pl011: Use correct accessors
Hi Michal,
> -----Original Message-----
> Subject: [PATCH 3/4] xen/arm: pl011: Use correct accessors
>
> At the moment, we use 32-bit only accessors (i.e. readl/writel) to match
> the SBSA v2.x requirement. This should not be the default case for normal
> PL011 where accesses shall be 8/16-bit (max register size is 16-bit).
> There are however implementations of this UART that can only handle 32-bit
> MMIO. This is advertised by dt property "reg-io-width" set to 4.
>
> Introduce new struct pl011 member mmio32 and replace pl011_{read/write}
> macros with static inline helpers that use 32-bit or 16-bit accessors
> (largest-common not to end up using different ones depending on the actual
> register size) according to mmio32 value. By default this property is set
> to false, unless:
> - reg-io-width is specified with value 4,
> - SBSA UART is in use.
>
> For now, no changes done for ACPI due to lack of testing possibilities
> (i.e. current behavior maintained resulting in 32-bit accesses).
>
> Signed-off-by: Michal Orzel <michal.orzel@xxxxxxx>
I've tested this patch on top of today's staging on FVP arm32 and arm64 and
confirm this patch will not break existing functionality. So:
Tested-by: Henry Wang <Henry.Wang@xxxxxxx>
Kind regards,
Henry
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