Re: [PATCH v1 2/3] ARM: GICv3 ITS: do not invalidate memory while sending a command

[Julien Grall <julien@xxxxxxx>]

On 19/09/2023 15:36, Volodymyr Babchuk wrote:
> Julien Grall <julien@xxxxxxx> writes:
> > On 19/09/2023 12:28, Volodymyr Babchuk wrote:
> > > There is no need to invalidate cache entry because we just wrote into a
> > > memory region. Writing itself guarantees that cache entry is valid.
> > The goal of invalidate is to remove the line from the cache. So I
> > don't quite understand the reasoning here.
> Well, I may be wrong, but what is the goal in removing line from the
> cache? As I see this, we want to be sure that ITS sees data written in
> the memory, so we should flush a cache line. But why do we need to
> remove it from CPU's cache?
I don't exactly know. From a brief look I agree with you. However, our 
driver is based on Linux where the clean & invalidate is also used. So I 
am a little be cautious to remove it.
The way forward would be to ask the Marc Zyngier (GICv3 maintainer) why 
it was added in Linux. Then we can decide whether this can be removed in 
Xen.
Cheers,

--
Julien Grall