[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH] arm/gicv3: Fix ICH_VTR_EL2.ListRegs mask
- To: Michal Orzel <michal.orzel@xxxxxxx>
- From: Bertrand Marquis <Bertrand.Marquis@xxxxxxx>
- Date: Tue, 10 Sep 2024 08:49:58 +0000
- Accept-language: en-GB, en-US
- Arc-authentication-results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 63.35.35.123) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=arm.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dkim=[1,1,header.d=arm.com] dmarc=[1,1,header.from=arm.com])
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none
- Arc-message-signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=idv1nK4Gptf+918VwwTFDLlODafrxluPiCYAOpZTlK8=; b=b02u87nPzuJXC1BxNZgMKFwt2BZPP+RW1Kh55KGerR5lh68MiZEURNlFlrKmGrxIevpD5E2U8RrJ00bSObX4Boa1rX4bqjiMTmi00NuAn9Xdvm1fZU6DO8qiORLSJms+Yn5RoNBlZLpDyYAo3sBBr8sYdyv6wYeqWh4wvnO6ffQowiUxUek/L8VU26Nqvwgpu6r7N0ffAowZofNFgDMoBg8mQdztZdc2Gf3EjdfI7xF6paf0xNCVMfmROlWmT3o7qFRVLq+nM5D/h164Fxh5GdNHBh2B2NRGMGSoISorfsvB2TIXsdTOhHf2MshbRye3GF5TQbWbJbeN7dm6mZYhpA==
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=idv1nK4Gptf+918VwwTFDLlODafrxluPiCYAOpZTlK8=; b=SWXgpE/YVydLHHIk2ejA7GYnADqiBOdRSYNwkYEK/vq4F3gFduT0Odzk6AG2oXqMMttiU+Be5Md40APHHud+ad+0au779lv1uz00vHhPDL3bjnMgC02P0uMcfaHvWTNJmlTl8B2MJrEVVlCqsQC+5mcKupcXCsVSCd+GYAnEm918q+cFx/6Fd6At51Agw58YAdYn3hRzwpxw/cHXoNhakJmAMjPPejkGGcVRvGLoZWDJtl7jRn79KayHn+kQ8xpJ4QStPwW5tqF9bIkuAla+WpJ6PFSGC4IzNZG/5Zxk5vW9x9T+9JuX1kipQIwC8rrmzGyIiIanUDn++BF5khwoCA==
- Arc-seal: i=2; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=pass; b=etlRduFgU/ais4G+rmKcC9hO64+rd6Kq1XTBVPv0PeEEJxo7FcjoyhXwqtlQ1/6w95iw0S5mn7gEJrjo+jL1cwU0kvUxXa9Nf9DcdExfi5l73YaPt7w3cJOviqoGOle0BGuInGAHz61PmfReGndWiEjCwDJrwgkc6kBxhTCC559MB3cOAy7WQLZ6XBUeiFPoFOBMB2aj18Lft1gddRGvTfL+h3o0ftBxVDhbqaWomfrNB+WLnGxysDspPib1BBZ0rjjpTkhQGcohKeaXXORNhc4cf8Xixfu8TuFu+13znPOMOmTsgxPVdsHMIQQFeUhbveWIxSd2pbztBamh+EGUow==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=JB76P5lIS4ZihXEdSeYb7z5iHNrI4RDan5PWJz7OlLUZydIPGj1+fzm6NL8VJSYiGR/fLM/vRu1B12zXz+sc3ykblGpeDrnWM1rOhmXFAJgL7JQTpU50sQAsG26Cw8ZRI1uWipbrD3qYzm6XHyZuIxcaKSAZc7fkROpPxFujXMVSrAg1dLpPmpvma8p9c/62DZj5ZYFdMxlkbVKElSioyYzr9j/d1BeUE0orldD4JnVq30zqLGXVj04pcJ/YUgPS4Mr/fc1/1EpvkjwKp5vWRhLmiSIhJDkVW15cwzVpT+e5td1qMPIukYLYrDE6SGig364D/AzI0pHOpDUsz7s+Zg==
- Authentication-results-original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com;
- Cc: Xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, Julien Grall <julien@xxxxxxx>, Volodymyr Babchuk <Volodymyr_Babchuk@xxxxxxxx>
- Delivery-date: Tue, 10 Sep 2024 08:53:38 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
- Nodisclaimer: true
- Original-authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com;
- Thread-index: AQHa/fvtz5D3yIGWFECvg14op8Y9NrJQwNAA
- Thread-topic: [PATCH] arm/gicv3: Fix ICH_VTR_EL2.ListRegs mask
Hi Michal,
> On 3 Sep 2024, at 14:21, Michal Orzel <michal.orzel@xxxxxxx> wrote:
>
> According to GIC spec IHI 0069H.b (12.4.9), the ListRegs field of
> ICH_VTR_EL2 can have value between 0b00000..0b01111, as there can
> be maximum 16 LRs (field value + 1). Fix the mask used to extract this
> value which wrongly assumes there can be 64 (case for GICv2).
>
> Fixes: bc183a0235e0 ("xen/arm: Add support for GIC v3")
> Signed-off-by: Michal Orzel <michal.orzel@xxxxxxx>
Nice finding.
Reviewed-by: Bertrand Marquis <bertrand.marquis@xxxxxxx>
Cheers
Bertrand
> ---
> xen/arch/arm/include/asm/gic_v3_defs.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/xen/arch/arm/include/asm/gic_v3_defs.h
> b/xen/arch/arm/include/asm/gic_v3_defs.h
> index 227533868f8d..2af093e774e5 100644
> --- a/xen/arch/arm/include/asm/gic_v3_defs.h
> +++ b/xen/arch/arm/include/asm/gic_v3_defs.h
> @@ -189,7 +189,7 @@
> #define ICH_LR_GRP1 (1ULL << 60)
> #define ICH_LR_HW (1ULL << 61)
>
> -#define ICH_VTR_NRLRGS 0x3f
> +#define ICH_VTR_NRLRGS 0xf
> #define ICH_VTR_PRIBITS_MASK 0x7
> #define ICH_VTR_PRIBITS_SHIFT 29
>
> --
> 2.25.1
>
|
