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Re: Slow (higher scheduling latency?) system after S3 - regression 4.17 -> 4.19 ?


  • To: Jan Beulich <jbeulich@xxxxxxxx>
  • From: Marek Marczykowski-Górecki <marmarek@xxxxxxxxxxxxxxxxxxxxxx>
  • Date: Tue, 7 Apr 2026 14:01:20 +0200
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  • Cc: xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>, Jürgen Groß <jgross@xxxxxxxx>, Roger Pau Monné <roger.pau@xxxxxxxxxx>
  • Delivery-date: Tue, 07 Apr 2026 12:01:33 +0000
  • Feedback-id: i1568416f:Fastmail
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>

On Tue, Apr 07, 2026 at 08:14:42AM +0200, Jan Beulich wrote:
> On 03.04.2026 15:55, Marek Marczykowski-Górecki wrote:
> > On Thu, Apr 02, 2026 at 03:02:15PM +0200, Marek Marczykowski-Górecki wrote:
> >> On Fri, Mar 27, 2026 at 01:47:55PM +0100, Marek Marczykowski-Górecki wrote:
> >>> Some further observation, this time regarding timers:
> >>
> >> In the meantime Roger suggested it might be about C-states. So, I just
> >> tried booting with max_cstate=0. I got this:
> > 
> > We had a design session on this issue, and managed to find (thanks Roger!)
> > that adding:
> > 
> >     tsc_mode='always_emulate'
> > 
> > to the domU config fixes the issue. Now, the question is how to fix it
> > properly...
> 
> Seeing also the remarks on Matrix, what we will hence need to figure is what
> TSC parameters (of the system and/or the VM) change across suspend. As per
> Matrix everything looked at so far was apparently stable.

I added some more logging (based on 
https://sandpile.org/x86/msr.htm | grep TSC) - see attached debug patch.
The output before and after S3:

    ==> msr-before.txt <==
    (XEN) [  118.910886] MSR 00000010: 000000cd6d18d6c1
    (XEN) [  118.911110] MSR 0000003b: 0000000000000000
    (XEN) [  118.911331] MSR c0000103: 0000000000000000
    (XEN) [  118.911559] Fixup #GP[0000]: ffff82d04029ad8d 
[arch/x86/cpu/intel.c#debug_tsc+0x76/0x84] -> ffff82d04029ad83
    (XEN) [  118.912029] MSR 000006e0: 0000000000000000
    (XEN) [  118.912253] MSR 000000e7: 000000064cf8ec5e
    (XEN) [  118.912473] MSR 000000e8: 000000065d09c019
    (XEN) [  118.912687] MSR 0000064e: 000000052ec83116


    ==> msr-after.txt <==
    (XEN) [  146.396099] MSR 00000010: 00000012fac68ccd
    (XEN) [  146.396329] MSR 0000003b: 0000000000000000
    (XEN) [  146.396553] MSR c0000103: 0000000000000000
    (XEN) [  146.396777] Fixup #GP[0000]: ffff82d04029ad8d 
[arch/x86/cpu/intel.c#debug_tsc+0x76/0x84] -> ffff82d04029ad83
    (XEN) [  146.397248] MSR 000006e0: 0000000000000000
    (XEN) [  146.397470] MSR 000000e7: 00000001e41a578a
    (XEN) [  146.397690] MSR 000000e8: 000000017dc5b211
    (XEN) [  146.397909] MSR 0000064e: 000000014eddbe8f

Nothing interesting here...

What other values would make sense to compare?

-- 
Best Regards,
Marek Marczykowski-Górecki
Invisible Things Lab

Attachment: 0001-DEBUG-TSC.patch
Description: Text document

Attachment: signature.asc
Description: PGP signature


 


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