Re: [Xen-users] Enabling AMD-Vi IOMMU panics Xen

[Kyösti Mälkki <kyosti.malkki@xxxxxxxxx>]

On Thu, Apr 14, 2016 at 9:29 PM, 小太 <nospam@xxxxxxxx> wrote:

On Sat, Apr 9, 2016 at 10:19 PM, kmalkki <kyosti.malkki@xxxxxxxxx> wrote:

0001-IOMMU.patch

+++ b/src/cpu/amd/pi/heapmanager.c
@@ -36,7 +36,7 @@ void EmptyHeap(void)
     memset(BiosManagerPtr, 0, BIOS_HEAP_SIZE);
 }
 
-#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) && !defined(__PRE_RAM__)
+#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI_00730F01) && !defined(__PRE_RAM__)

What does this change do? It doesn't look like it's used by the IOMMU

 

See Family 16h Model 30h-3Fh registers D0F0x98_x26 and D0F0x98_x27. AGESA makes a request to reserve 128 bytes of physical memory that is safe for DMA-like operation.

 

0002-apu2.patch

+++ b/src/mainboard/pcengines/apu2/agesawrapper.c
@@ -468,6 +467,10 @@ AGESA_STATUS agesawrapper_amdinitlate(void)
     /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */
     AmdCreateStruct(&AmdParamStruct);
     AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr;
+
+    AmdLateParams->GnbLateConfiguration.GnbIoapicId = 0x05;
+    AmdLateParams->GnbLateConfiguration.FchIoapicId = 0x04;

Looks like I forgot to add these two lines to my own version of the patch! This adds the missing IOAPIC entries to the IVRS table.

To think I searched both the BKDG and IOMMU spec but forgot the AGESA documentation...

That said, even with your additions to the patch, I tried setting ivrs_iommu[5] to all the "non-device" devices returned from lspci (i.e., devices 00, 02, 14 and 18 and all their individual functions), I still got the same panic at hvm_find_io_handler+0x6f that you can see at the bottom of "iommu=no-intremap.log" (http://lists.xen.org/archives/html/xen-users/2016-03/txtkvG3rJp7O1.txt) in my first post.
So now I'm thinking the IVRS table isn't wrong (with the northbridge IOAPIC at 00:00.0), but there might be an issue with the IOMMU itself or Xen.

The IVHD entry ranges are wrong.

[048h 0072   1]                   Entry Type : 03
[049h 0073   2]                    Device ID : 0008
[04Bh 0075   1]                 Data Setting : 00

[04Ch 0076   1]                   Entry Type : 04
[04Dh 0077   2]                    Device ID : FFFE
[04Fh 0079   1]                 Data Setting : 00

This range is 0:1.0 to ff.1f.6. The very last function is not in the range?

[050h 0080   1]                   Entry Type : 43
[051h 0081   2]                    Device ID : FF00
[053h 0083   1]                 Data Setting : 00
[054h 0084   1]                     Reserved : 00
[055h 0085   2]        Source Used Device ID : 00A4
[057h 0087   1]                     Reserved : 00

[058h 0088   1]                   Entry Type : 04
[059h 0089   2]                    Device ID : FFFF
[05Bh 0091   1]                 Data Setting : 00

This range is ff:0.0 to ff:1f.7. The source device id of 0:14.4 was previously a PCI bridge so this entry is bogus for this family of APU. Should we describe each PCIe root port / bridge in this table?

Regards,

Kyösti Mälkki

_______________________________________________
Xen-users mailing list
Xen-users@xxxxxxxxxxxxx
http://lists.xen.org/xen-users