Re: [Xen-devel] Future support of 5-level paging in Xen:wq

[Andrew Cooper <andrew.cooper3@xxxxxxxxxx>]

On 13/12/16 05:44, Li, Liang Z wrote:
>> Subject: RE: [Xen-devel] Future support of 5-level paging in Xen:wq
>>
>>> From: Li, Liang Z
>>> Sent: Tuesday, December 13, 2016 11:58 AM
>>>
>>> Hi All,
>>>
>>> We are now working on enabling 5 level paging & 5 level EPT for XEN.
>>> We need the community's opinions about the following aspects:
>>>
>>> 1.  Should we enable 5 level paging for PV guest ? (You are
>>> discussing) 2.  Should we make the 5 level paging and 4 level paging
>> supported with one binary?
>>> 3.  When should the 5 level EPT be enabled?
>> Isn't it as usual i.e. let's enable once the spec is published? Or could you
>> elaborate any concern of asking this question?
>>
> The concern is the performance vs complexity . Walk the 5 level EPT is slower 
> than the 4 level EPT because
>  It needs to access the memory one more time.
> We can chose to enable 5 level EPT as long as the CPU support, or only when 
> it's needed, e.g.
>  to support a guest with huge amount of  memory(beyond 48bit physical address 
> can support),
> or when the host has a small amount of memory present.
>
> The former is simple and straight forward, and the latter is better for 
> performance but add extra
> mechanism  to choose the proper EPT level used. Which one to use may 
> dependent on the performance
> gap.

In this case, at the point that we support 5 level EPT, we are going to
have to support hardware with a walk length of 3 as well as 4, so we
will have code to deal with both.

There is nothing to be gained by using a walk length of 4 when 3 will
do, and a performance penalty for doing so.

I think it would be entirely reasonable (and hopefully straightforward)
to choose the walk length based on the toolstack-provided CPUID policy
maxphysaddr.  (Certainly more straightforward than getting Xen's memory
management code to understand 5-level plain pagetables.)

~Andrew

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