Re: [Xen-devel] [PATCH v3 01/14] x86/cpu: Create Hygon Dhyana architecture support file

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 27.03.19 at 09:14, <puwen@xxxxxxxx> wrote:
> On 2019/3/26 23:49, Jan Beulich wrote:
>> On 25.03.19 at 14:29, <puwen@xxxxxxxx> wrote:
>>> @@ -116,6 +121,9 @@ bool __init probe_cpuid_faulting(void)
>>>     uint64_t val;
>>>     int rc;
>>>   
>>> +   if(boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
>>> +           return false;
>>> +
>>>     if ((rc = rdmsr_safe(MSR_INTEL_PLATFORM_INFO, val)) == 0)
>> 
>> Isn't this similarly true for AMD, in which case adding both at the
> 
> There is no MSR_INTEL_PLATFORM_INFO for AMD family 17h and Hygon family
> 18h. Reading this MSR will stall on Hygon system. I don't know if it
> would successfully returned when reading it on AMD system.

What do you mean by "stall"? Reading an unimplemented MSR
should produce #GP(0).

>> same time in a separate patch would seem better? Yet then again -
> 
> In a separate patch is fine.
> 
>> did you look at the description of the commit moving the function
>> here (6e2fdc0f89 ["x86: Common cpuid faulting support"])? Hence
>> if anything this would need qualifying by !cpu_has_hypervisor.
> 
> Then it would be like this:
>       if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON &&
>           !cpu_has_hypervisor)
>               return false;

Right, plus perhaps said AMD addition, unless Andrew objects to it
for some reason.

Jan



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