[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [Xen-devel] [PATCH RFC] x86emul: unconditionally deliver #UD for LWP insns
On 18.07.2019 11:30, Andrew Cooper wrote: > On 18/07/2019 10:18, Jan Beulich wrote: >> On 17.07.2019 19:09, Andrew Cooper wrote: >>> On 17/07/2019 14:07, Jan Beulich wrote: >>>> On 17.07.2019 13:42, Andrew Cooper wrote: >>>>> On 17/07/2019 07:42, Jan Beulich wrote: >>>>>> With AMD apparently having abandoned XOP encoded insns, another option >>>>>> would seem to be to simply wire all unrecognized ones into #UD (rather >>>>>> then returning UNIMPLEMENTED/UNRECOGNIZED). >>>>> There are still some XOP instructions which actually work on Fam17h >>>>> processors, if you ignore CPUID and go blindly executing. >>>>> >>>>> Given no official statement that XOP is dead, I'd keep the support we >>>>> currently have. >>>> Then my remark wasn't clear enough: I'm not suggesting to rip out >>>> XOP insn support we have. I'm instead considering whether to wire >>>> all unsupported XOP encodings into #UD (rather than return >>>> UNIMPLEMENTED/UNRECOGNIZED for them), not just the LWP ones. >>> Ah, in which case, no. Turning all unknown instructions into >>> EXCEPTION/#UD will break introspection, which uses UNRECOGNISED to cover >>> the gaps in the emulator by single-stepping the vcpu. >> But there are no gaps: > > [F]XSAVE et al, VT-x, SVM to name several gaps. > > Not to mention running current versions of Xen on newer hardware. None of these are XOP encoded. I've never been considering to wire everything into #UD. Jan _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxxxxxxxxx https://lists.xenproject.org/mailman/listinfo/xen-devel
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